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FUNCTIONAL DESCRIPTION
B. INTERRUPT
IDENTIFICATION REGISTER
+------+
D7 | FFE |----- FIFO enable (FIFO only)
+------+
D6 | 0 |
+------+
D5 | 0 |
+------+
D4 | 0 |
+------+
D3 | IID2 |--+
+------+ |
D2 | IID1 | +-- Interrupt identification
+------+ |
D1 | IID0 |--+
+------+
D0 | IP |----- Interrupt pending
+------+
Figure 4. Interrupt identification register bit
definitions.
FFE - FIFO Enable:
When logic 1, indicates FIFO mode enabled.
IIDx - Interrupt Identification:
Indicates highest priority interrupt pending if
any. See IP and figure 5. NOTE: IID2 is always
a logic 0 in character mode.
IP - Interrupt Pending:
When logic 0, indicates that an interrupt is
pending and the contents of the interrupt
identification register may be used to determine
the interrupt source. See IIDx and figure 5.
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