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FUNC
TIONAL DESCRIPTION
+-------------------+----------+----------------------+
| IID2 IID1 IID0 IP | Priority | Interrupt Type |
+-------------------+----------+----------------------+
| x x x 1 | N/A | None |
| 0 1 1 0 | Highest | Receiver Line Status |
| 0 1 0 0 | Second | Received Data Ready |
| 1 1 0 0 | Second | Character Timeout |
| | | (FIFO only) |
| 0 0 1 0 | Third | Transmitter Holding |
| | | Register Empty |
| 0 0 0 0 | Fourth | MODEM Status |
+-------------------+----------+----------------------+
Figure 5. Interrupt identification bit definitions.
Receiver Line Status:
Indicates overrun, parity, or framing errors or
break interrupts. The interrupt is cleared by
reading the line status register.
Received Data Ready:
Indicates receive data available. The interrupt
is cleared by reading the receiver buffer
register.
FIFO mode:
Indicates the receiver FIFO trigger level has
been reached. The interrupt is reset when the
FIFO drops below the the trigger level.
Character Timeout: (FIFO mode only)
Indicates no characters have been removed from or
input to the receiver FIFO for the last four
character times and there is at least one
character in the FIFO during this time. The
interrupt is cleared by reading the receiver
FIFO.
Transmitter Holding Register Empty:
Indicates the transmitter holding register is
empty. The interrupt is cleared by reading the
interrupt identification register or writing to
the transmitter holding register.
MODEM Status:
Indicates clear to send, data set ready, ring
indicator, or data carrier detect have changed
state. The interrupt is cleared by reading the
MODEM status register.
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