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FUNCTIONAL DESCRIPTION
III. 16550 FUNCTIONAL DESCRIPTION
The 16550 is an upgrade of the standard 16450
Asynchronous Communications Element (ACE). Designed to
be compatible with the 16450, the 16550 enters the
character mode on reset and in this mode will appear as a
16450 to user software. An additional mode, FIFO mode,
can be selected to reduce CPU overhead at high data
rates. The FIFO mode increases performance by providing
two internal 16-byte FIFOs (one transmit and one receive)
to buffer data and reduce the number of interrupts issued
to the CPU.
Other features of the 16550 include:
Programmable baud rate, character length, parity,
and number of stop bits
Automatic addition and removal of start, stop, and
parity bits
Independent and prioritized transmit, receive and
status interrupts
Transmitter clock output to drive receiver logic
External receiver clock input
The following pages provide a brief summary of the
internal registers available within the 16550 ACE. The
registers are addressed as shown in figure 2 below.
+---------------+-----------------------------------+
| DLAB A2 A1 A0 | REGISTER DESCRIPTION |
+---------------+-----------------------------------+
| 0 0 0 0 | Receive buffer (read) |
| | Transmit holding register (write) |
| 0 0 0 1 | Interrupt enable |
| x 0 1 0 | Interrupt identification (read) |
| | FIFO control (write) |
| x 0 1 1 | Line control |
| x 1 0 0 | MODEM control |
| x 1 0 1 | Line status |
| x 1 1 0 | MODEM status |
| x 1 1 1 | Scratch |
| 1 0 0 0 | Divisor latch (least significant) |
| 1 0 0 1 | Divisor latch (most significant) |
+---------------+-----------------------------------+
Figure 2. Internal register map for 16550 ACE. DLAB is
accessed through the Line Control Register.
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