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EM78P447N
8-Bit Microcontroller with OTP ROM
32 •
Product Specification (V1.1) 03.30.2005
(This specification is subject to change without further notice)
INSTRUCTION
BINARY
HEX MNEMONIC OPERATION STATUS AFFECTED
0 0101 10rr rrrr 05rr DJZA R
R-1 → A, skip if zero
None
0 0101 11rr rrrr 05rr DJZ R
R-1 → R, skip if zero
None
0 0110 00rr rrrr 06rr RRCA R
R(n) → A(n-1),
R(0) → C, C → A(7)
C
0 0110 01rr rrrr 06rr RRC R
R(n) → R(n-1),
R(0) → C, C → R(7)
C
0 0110 10rr rrrr 06rr RLCA R
R(n) → A(n+1),
R(7) → C, C → A(0)
C
0 0110 11rr rrrr 06rr RLC R
R(n) → R(n+1),
R(7) → C, C → R(0)
C
0 0111 00rr rrrr 07rr SWAPA R
R(0-3) → A(4-7),
R(4-7) → A(0-3)
None
0 0111 01rr rrrr 07rr SWAP R
R(0-3) ↔ R(4-7)
None
0 0111 10rr rrrr 07rr JZA R
R+1 → A, skip if zero
None
0 0111 11rr rrrr 07rr JZ R
R+1 → R, skip if zero
None
0 100b bbrr rrrr 0xxx BC R,b
0 → R(b)
None <Note2>
0 101b bbrr rrrr 0xxx BS R,b
1 → R(b)
None <Note3>
0 110b bbrr rrrr 0xxx JBC R,b if R(b)=0, skip None
0 111b bbrr rrrr 0xxx JBS R,b if R(b)=1, skip None
1 00kk kkkk kkkk 1kkk CALL k
PC+1 → [SP],
(Page, k) → PC
None
1 01kk kkkk kkkk 1kkk JMP k
(Page, k) → PC
None
1 1000 kkkk kkkk 18kk MOV A,k
k → A
None
1 1001 kkkk kkkk 19kk OR A,k
A ∨ k → A
Z
1 1010 kkkk kkkk 1Akk AND A,k
A & k → A
Z
1 1011 kkkk kkkk 1Bkk XOR A,k
A ⊕ k → A
Z
1 1100 kkkk kkkk 1Ckk RETL k
k → A, [Top of Stack] → PC
None
1 1101 kkkk kkkk 1Dkk SUB A,k
k-A → A
Z,C,DC
1 1110 0000 010 1E02 INT
PC+1 → [SP], 002H → PC
None
1 1111 kkkk kkkk 1Fkk ADD A,k
k+A → A
Z,C,DC
NOTE
This instruction is applicable to IOC5 ~ IOC7, IOCB, IOCE, IOCF only.
This instruction is not recommended for R3F operation.
This instruction cannot operate under R3F.