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Power Management
40 Datasheet
4.3.1 CKE Power-Down
The CKE input land is used to enter and exit different power-down modes. The memory
controller has a configurable activity timeout for each rank. When no reads are present
to a given rank for the configured interval, the memory controller will transition the
rank to power-down mode.
The memory controller transitions the DRAM to power-down by de-asserting CKE and
driving a NOP command. The memory controller will tri-state all DDR interface lands
except CKE (de-asserted) and ODT while in power-down. The memory controller will
transition the DRAM out of power-down state by synchronously asserting CKE and
driving a NOP command.
When CKE is off, the internal DDR clock is disabled and the DDR power is significantly
reduced.
The DDR defines three levels of power-down:
• Active power-down: This mode is entered if there are open pages when CKE is de-
asserted. In this mode the open pages are retained. Existing this mode is 3 – 5
DCLK cycles.
• Pre-charge power-down fast exit: This mode is entered if all banks in DDR are pre-
charged when de-asserting CKE. Existing this mode is 3 – 5 DCLK cycles. Difference
from the active power-down mode is that when waking up all page-buffers are
empty.
• Pre-charge power-down slow exit: In this mode the data-in DLLs on DDR are off.
Existing this mode is 3 – 5 DCLK cycles until the first command is allowed, but
about 16 cycles until first data is allowed.
4.3.2 Self-Refresh
The Power Control Unit (PCU) may request the memory controller to place the DRAMs
in self-refresh state. Self-refresh per channel is supported. The BIOS can put the
channel in self-refresh if software remaps memory to use a subset of all channels. Also,
processor channels can enter self-refresh autonomously without a PCU instruction
when the package is in a package C0 state.
4.3.2.1 Self-Refresh Entry
Self-refresh entrance can be either disabled or triggered by an idle counter. Idle
counter always clears with any access to the memory controller and remains clear as
long as the memory controller is not drained. As soon as the memory controller is
drained, the counter starts counting. When it reaches the idle-count, the memory
controller will place the DRAMs in self-refresh state.
Power may be removed from the memory controller core at this point. But V
CCD
supply
(1.5V or 1.35V) to the DDR I/O must be maintained.