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Signal Descriptions
48 Datasheet
PROCHOT_N
Processor Hot: PROCHOT_N will go active when the processor temperature
monitoring sensor detects that the processor has reached its maximum safe
operating temperature. This indicates that the processor Thermal Control Circuit
has been activated, if enabled. This signal can also be driven to the processor to
activate the Thermal Control Circuit. This signal is sampled after PWRGOOD
assertion.
If PROCHOT_N is asserted at the de-assertion of RESET_N, the processor will tri-
state its outputs.
PWRGOOD
Power Good: This is a processor input. The processor requires this signal to be a
clean indication that BCLK, V
TTA
/V
TTD
, V
SA
, V
CCPLL
, and V
CCD_01
, and V
CCD_23
supplies are stable and within their specifications.
“Clean” implies that the signal will remain low (capable of sinking leakage
current), without glitches, from the time that the power supplies are turned on
until the supplies come within specification. The signal must then transition
monotonically to a high state.
PWRGOOD can be driven inactive at any time, but clocks and power must again
be stable before a subsequent rising edge of PWRGOOD. PWRGOOD transitions
from inactive to active when all supplies except V
CC
are stable. V
CC
has a VBOOT
of zero volts and is not included in PWRGOOD indication in this phase. However,
for the active to inactive transition, if any processor power supply (V
CC
, V
TTA
/V
TTD
,
V
SA
, V
CCD
, or V
CCPLL
) is about to fail or is out of regulation, the PWRGOOD is to be
negated.
The signal must be supplied to the processor. It is used to protect internal circuits
against voltage sequencing issues. It should be driven high throughout boundary
scan operation.
Note: V
CC
has a VBOOT setting of 0.0V and is not included in the PWRGOOD
indication and VSA has a Vboot setting of 0.9V.
RESET_N
Reset: Asserting the RESET_N signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. Some
PLL and error states are not effected by reset and only PWRGOOD forces them to
a known state.
SAFE_MODE_BOOT
Safe Mode Boot: Strap signal. SAFE_MODE_BOOT allows the processor to wake
up safely by disabling all clock gating. This allows BIOS to load registers or
patches if required. This signal is sampled after PWRGOOD assertion. The signal is
pulled down on the die (refer to Table 7-6 for details).
TEST[4:0]
Test: Test[4:0] must be individually connected to an appropriate power source or
ground through a resistor for proper processor operation.
THERMTRIP_N
Thermal Trip: Assertion of THERMTRIP_N indicates one of two possible critical
over-temperature conditions:
• The processor junction temperature has reached a level beyond which
permanent silicon damage may occur and
• The system memory interface has exceeded a critical temperature limit set by
BIOS.
Measurement of the processor junction temperature is accomplished through
multiple internal thermal sensors that are monitored by the Digital Thermal
Sensor (DTS). Simultaneously, the Power Control Unit (PCU) monitors external
memory temperatures using the dedicated SMBus interface to the DIMMs. If any
of the DIMMs exceed the BIOS defined limits, the PCU will signal THERMTRIP_N to
prevent damage to the DIMMs. Once activated, the processor will stop all
execution and shut down all PLLs.
To further protect the processor, its core voltage (V
CC
), V
TTA
, V
TTD
, V
SA
, V
CCPLL
,
V
CCD
supplies must be removed following the assertion of THERMTRIP_N. Once
activated, THERMTRIP_N remains latched until RESET_N is asserted. While the
assertion of the RESET_N signal may de-assert THERMTRIP_N, if the processor's
junction temperature remains at or above the trip level, THERMTRIP_N will again
be asserted after RESET_N is de-asserted. This signal can also be asserted if the
system memory interface has exceeded a critical temperature limit set by BIOS.
This signal is sampled after PWRGOOD assertion.
Table 6-12. Processor Asynchronous Sideband Signals (Sheet 2 of 3)
Signal Name Description