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Datasheet 59
Electrical Specifications
Table 7-5. Signal Groups (Sheet 1 of 3)
Differential /
Single Ended
Buffer Type Signals
1
DDR3 Reference Clocks
2
Differential SSTL Output DDR{0/1/2/3}_CLK_D[N/P][3:0]
DDR3 Command Signals
2
Single ended
SSTL Output
DDR{0/1/2/3}_BA[2:0]
DDR{0/1/2/3}_CAS_N
DDR{0/1/2/3}_MA[15:00]
DDR{0/1/2/3}_MA_PAR
DDR{0/1/2/3}_RAS_N
DDR{0/1/2/3}_WE_N
CMOS1.5v Output DDR_RESET_C{01/23}_N
DDR3 Control Signals
2
Single ended
CMOS1.5v Output
DDR{0/1/2/3}_CS_N[9:0]
DDR{0/1/2/3}_ODT[5:0]
DDR{0/1/2/3}_CKE[5:0]
Reference Output DDR_VREFDQTX_C{01/23}
Reference Input
DDR_VREFDQRX_C{01/23}
DDR{01/23}_RCOMP[2:0]
DDR3 Data Signals
2
Differential SSTL Input/Output DDR{0/1/2/3}_DQS_D[N/P][17:00]
Single ended
SSTL Input/Output DDR{0/1/2/3}_DQ[63:00]
SSTL Input DDR{0/1/2/3}_PAR_ERR_N
DDR3 Miscellaneous Signals
2
Single ended CMOS1.5v Input DRAM_PWR_OK_C{01/23}
PCI Express* Port 1, 2, and 3 Signals
Differential PCI Express* Input
PE1A_RX_D[N/P][3:0]
PE1B_RX_D[N/P][7:4]
PE2A_RX_D[N/P][3:0]
PE2B_RX_D[N/P][7:4]
PE2C_RX_D[N/P][11:8]
PE2D_RX_D[N/P][15:12]
PE3A_RX_D[N/P][3:0]
PE3B_RX_D[N/P][7:4]
PE3C_RX_D[N/P][11:8]
PE3D_RX_D[N/P][15:12]
Differential PCI Express* Output
PE1A_TX_D[N/P][3:0]
PE1B_TX_D[N/P][7:4]
PE2A_TX_D[N/P][3:0]
PE2B_TX_D[N/P][7:4]
PE2C_TX_D[N/P][11:8]
PE2D_TX_D[N/P][15:12]
PE3A_TX_D[N/P][3:0]
PE3B_TX_D[N/P][7:4]
PE3C_TX_D[N/P][11:8]
PE3D_TX_D[N/P][15:12]