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Technical Product Specification 23
Order #273817
Intel NetStructure
®
MPCBL0001 High Performance Single Board Computer
Contents
2.2.4.2 Real-Time Clock
The MPCBL0001 SBC real-time clock is integrated into the ICH3. It is derived from a 32.768 KHz
crystal with the following specifications:
• Frequency tolerance @ 25 ºC: ±20ppm
• Frequency stability: maximum of -0.04ppm/(ΔºC)
2
• Aging ΔF/f (1
st
year @ 25 ºC): ±3ppm
• ±20ppm from 0-55 ºC and aging 1ppm/year
The real-time clock is powered by a 0.22F SuperCap* capacitor when main power is not applied to
the board. This capacitor powers the real-time clock for a minimum of two hours while external
power is removed from the MPCBL0001 SBC.
See Section 3.13, “Watchdog Timers (WDTs)” on page 64 for information about the real-time
clock timers.
2.2.4.3 Timer0 Capabilities
Timer0, integrated inside the ICH3, is an 8254 compatible timer. This timer is set up to generate a
periodic waveform that creates the edge for the timer0 interrupt. The interrupt is received by the
ICH3 APIC and communicated to the CPU(s).
MPCBL0001 provides a high-precision 14.318 MHz crystal clock source as the reference for the
timer0 counters. To improve timing accuracy, the crystal used is a low-PPM, high-stability
component with the following specifications:
• Frequency tolerance (25º C): ±10ppm
• Temperature characteristics (-10º C to +60º C): ±5ppm
• Aging: ±1ppm per year max
This timer does not operate when board power is removed.
2.2.4.4 Gigabit Ethernet (U13)
The MPCBL0001 SBC implements two Gigabit Ethernet interfaces, each of which is routed to the
fabric/switch slot through the backplane (J23, see page 85). There are no direct, external Ethernet
ports included on the SBC board. Each Ethernet connection utilizes an 82546 Dual Gigabit
Ethernet Controller, allowing support for 1000Mbits/s, 100Mbits/s and 10Mbits/s data rates.
The 82546 controller is optimized for designs using the PCI and the emerging PCI-X bus interface
extension. The MPCBL0001 SBC has a 133 MHz PCI-X bus connection. The integrated physical
layer circuitry (PHY) provides an IEEE 802.3 Ethernet Interface for 1000Base-T, 100Base-TX,
and 10Base-T applications.
Features include:
• 32/64-bit 33/66 MHz, PCI Rev 2.2 compliant interface
• Host interface also compliant with the PCI-X addendum, Rev 1.0a, from 50 to 133 MHz
• Supports 64-bit addressing
• Efficient PCI bus master operation, supported by optimized internal DMA controller