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DS33Z41 Quad IMUX Ethernet Mapper
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8.9.1 Microprocessor Requirements
Link aggregation requires an external host microprocessor to issue instructions and to monitor the IMUX function
of the DS33Z41. The host microprocessor is responsible for the following tasks to open a transmit channel:
• Configuring GL.IMXCN
to control the links participating in the aggregation.
• Issuing a link start command through GL.IMXC
.
• Monitoring the ITSYNC1-4 status from GL.IMXSS
or GL.IMXSLS.
• Monitoring GL.IMXDFDELS
.IDDELS0 to ensure that differential delay is not larger than 7.75ms.
• Setting GL.IMXCN
.SENDE to begin transmitting data after all links are synchronized.
• Resetting the queue pointers in GL.C1QPR
.
• Monitoring the TOOFLS1-4 status from GL.IMXOOFLS
to restart handshaking procedure if needed.
The host microprocessor is also responsible for the following tasks to open a receive channel:
• Monitoring the status of IRSYNC1-4 and setting GL.IMXCN
.RXE to receive data.
When in the data phase, if any of the links are detected to be out of frame (OOF), data will be corrupted. The link
initialization procedure must be initiated again. Note that the serial HDLC or X.86 encoded data is sent on 4 T1/E1
links, each link will not have separate HDLC/X.86 encoded data. The HDLC/X.86 encoding and decoding is data
is only available when the DS33Z41 has performed an IMUX function. Hence on the line the FCS for a given
HDLC packet could transport on a separate link than the HDLC data.