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DS33Z41 Quad IMUX Ethernet Mapper
73 of 167
Register Name:
GL.CON1
Register Description:
Connection Register for Ethernet Interface 1
Register Address:
0Eh
Bit # 7 6 5 4 3 2 1 0
Name — — — — — — — LINE1[0]
Default 0 0 0 0 0 0 0 1
Bit 0: LINE1[0]. This bit is preserved to provide software compatibility with multiport devices. The LINE1[0] bit
selects the Ethernet port that is to be connected to the Serial Interface. Note that bidirectional connection is
assumed between the Serial and Ethernet Interfaces. The connection register and corresponding queue size
must be defined for proper operation. Writing a 0 to this register will disconnect the connection. When a
connection is disconnected, “1”s are sourced to the Serial Interface transmit and to the HDLC receiver and the
clocks to the HDLC transmitter/receiver are disabled.
Register Name:
GL.C1QPR
Register Description:
Connection 1 Queue Pointer Reset
Register Address:
12h
Bit #
7 6 5 4 3 2 1 0
Name
— — — — C1MRPRR C1HWPRR C1MHPR C1HRPR
Default
0 0 0 0 0 0 0 0
Bit 3: MAC Read Pointer Reset (C1MRPR). Setting this bit to 1 resets the receive queue read pointer for
connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
Bit 2: HDLC Write Pointer Reset (C1HWPR). Setting this bit to 1 resets the receive queue write pointer for
connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
Bit 1: HDLC Read Pointer Reset (C1MHPR). Setting this bit to 1 resets the transmit queue read pointer for
connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must clear
the bit before subsequent reset operations.
Bit 0: MAC Transmit Write Pointer Reset (C1HRPR). Setting this bit to 1 resets the transmit queue write pointer
for connection 1. This queue pointer must be reset after a disconnect and before a connection. The user must
clear the bit before subsequent reset operations.