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7.2 PCB Layout
7.2.2 Main Control Board (HBMC-3 PCB) (OKIPAGE 4m)
S W I
1 2
Short Plag
SP1
Plag Setting
A External EPROM is valid.
Mask ROM in the CPU is valid.B
Content
DIP Switch
Switch Setting
Content
SW1-1
SW1-2
UPPER SIDE*
UPPER SIDE*
LOWER SIDE
LOWER SIDE
AUTO I/F
FIX I/F (By SW2-2)
FIX PARALLEL I/F
FIX MAC I/F
*Default setting. Do not change.
Remarks
not used