Filter
Top Products
Philips Semiconductors
ISP1521
Hi-Speed USB hub controller
Product data Rev. 03 — 24 November 2004 39 of 53
9397 750 13702
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Table 43: Dynamic characteristics: high-speed source electrical characteristics
V
CC
= 3.0 V to 3.6 V; T
amb
=
−
40
°
Cto+70
°
C; test circuit Figure 21; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Driver characteristics
t
HSR
rise time 10 % to 90 % 500 - - ps
t
HSF
fall time 90 % to 10 % 500 - - ps
Clock timing
t
HSDRAT
data rate 479.76 - 480.24 Mbit/s
t
HSFRAM
microframe interval 124.9375 - 125.0625 µs
t
HSRFI
consecutive microframe interval
difference
1 - four high-speed
bit times
ns
Table 44: Dynamic characteristics: full-speed source electrical characteristics
V
CC
= 3.0 V to 3.6 V; T
amb
=
−
40
°
Cto+70
°
C; test circuit Figure 22; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Driver characteristics
t
FR
rise time C
L
= 50 pF; 10 % to 90 % of
|V
OH
− V
OL
|
4 - 20 ns
t
FF
fall time C
L
= 50 pF; 90 % to 10 % of
|V
OH
− V
OL
|
4 - 20 ns
t
FRFM
differential rise and fall time
matching
[1]
90 - 111.1 %
Z
DRV
driver output resistance for the driver that is not
high-speed capable
28 - 44 Ω
V
CRS
output signal crossover voltage
[1][2]
1.3 - 2.0 V
Data source timing
[2]
t
DJ1
source differential jitter for
consecutive transitions
see Figure 10
[1]
−3.5 - +3.5 ns
t
DJ2
source differential jitter for paired
transitions
see Figure 10
[1]
−4 - +4 ns
t
FEOPT
source SE0 interval of EOP see Figure 11 160 - 175 ns
t
FDEOP
source differential data-to-EOP
transition skew
see Figure 11 −2 - +5 ns
Receiver timing
[2]
t
JR1
receiver data jitter tolerance for
consecutive transitions
see Figure 12 −18.5 - +18.5 ns
t
JR2
receiver data jitter tolerance for
paired transitions
see Figure 12 −9 - +9 ns
t
FEOPR
receiver SE0 width accepted as EOP; see
Figure 11
82--ns
t
FST
width of SE0 interval during
differential transaction
rejected as EOP; see Figure 13 --14ns
Hub timing (downstream ports configured as full-speed)
[2]
t
FHDD
hub differential data delay (without
cable)
see Figure 14; C
L
=0pF --44ns