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HD49335NP/HNP
Rev.1.0, Feb.12.2004, page 18 of 29
Explanation of Serial Data of CDS Part
Serial data of CDS part are assigned to address H’F0 to H’F8. Functions are follows.
Address STD1[7:0] (L)
PGA gain
STD2[15:8] (H)
1 1 1 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14
D13
test_I1
• PGA gain (D0 to D7 of address H’F0)
Details are referred to page 5 block diagram.
At CDS_in mode: –2.36 dB + 0.132 dB × N (Log linear)
At ADC_in mode: 0.57 times + 0.01784 times × N (Times linear)
∗: Full-scale digital output is defined as 0 dB when 1 V is input.
Above PGA gain definition means input signal 1 Vp-p to CDS_in, and set N = 18 (correspond 2.36 dB), and then
PGA outputs the 2 V full-range, and also ADC out puts the full code (1023).
This mean offset gain of PGA has 6 dB – 2.36 dB = 3.64 dB, therefore it should be decided that how much dB add
on.
(1) Level dia explain
CDS PGA
0 dB when set N = 18 which correspond to 2.36 dB
ADC
(2) Level dia on the circuit
CDS PGA
3.64 dB + 0.132 dB × N
(CDS = 0 dB)
ADC
2 V 1023
(1.0 V)
(1.0 V) (2.0 V)
(1023)
Figure 9 Level Dia of PGA
• Test_I1 (D13 to D15 of address H’F0)
It controls the standard current of analog amplifier systems of CDS, PGA. Use data = 4 (D15 = 1) normally.
When data = 0, 50% current value with default
When data = 4, default
When data = 7, 150% current value with default
Address STD1[7:0] (L) STD2[15:8] (H)
1 1 1 1 0 0 0 1 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
SHA_fseltest_I2 SHSW_fsel
test0
MINV
LINV
STBY
SLP
• SLP and STBY (D0, D1 of address H’F1)
SLP: Stop the all circuit. Consumption current of CDS part is less than 10 µA.
Start up from offset calibration when recover is needed.
STBY: Only the standard voltage generating circuit is operated. Consumption current of CDS part is about 3 mA.
Allow 50 H time for feedback clamp is stabilized until recover.