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DISK DRIVE OPERATION
SpinPoint V40 Product Manual
97
6.7.4.2 Ultra DMA data burst timing requirements
Table 6-19 Ultra DMA data burst timing requirements
Mode 0
(ns)
Mode 1
(ns)
Mode 2
(ns)
Mode 3
(ns)
Mode 4
(ns)
Mode 5
(ns)
Name
min max min max min max min max min max min max
Comment
(see Notes 1 and 2)
t
2CYCTYP
240 160 120 90 60 40 Typical sustained average two cycle time
t
CYC
112 73 54 39 25 16.8 Cycle time allowing for asymmetry and
closk variations (from STROBE edge to
STROBE edge)
t
2CYC
230 154 115 86 57 38 Two cycle time allowing for clock
variations (from rising edge to next rising
edge or from falling edge to next falling
edge of STROBE)
t
DS
15 10 7 7 5 4.0 Data setup time at recipient
t
DH
5 5 5 5 5 4.6 Data hold time at recipient
t
DVS
70 48 30 20 6 4.8 Data valid setup time at sender (from data
valid until STROBE edge) (see Note 4)
t
DVH
6 6 6 6 6 4.8 Data valid hold time at sender (from
STROBE edge until data may become
invalid) (see Note 4)
t
FS
0 230 0 200 0 170 0 130 0 120 90 First STROBE time (for device to first
negate DSTROBE from STOP during a
data in burst)
t
LI
0 150 0 150 0 150 0 100 0 100 0 75 Limited interlock time (see Note 3)
t
MLI
20 20 20 20 20 20 Interlock time with minimum (see Note 3)
t
UI
0 0 0 0 0 0 Unlimited interlock time (see Note 3)
t
AZ
10 10 10 10 10 10 Maximum time allowed for output drivers
to release (from asserted or negated)
t
ZAH
20 20 20 20 20 20 Minimum delay time required for output
t
ZAD
0 0 0 0 0 Drivers to assert or negate (from released)
t
ENV
20 70 20 70 20 70 20 55 20 55 20 50 Envelope time (from DMACK- to STOP
and HDMARDY –during data in burst
initiation and from DMACK to STOP
during data out burst initiation
t
SR
50 30 20 NA NA NA STROBE-to-DMARDY-time (if
DMARDY- is negated before this long
after STROBE edge, the recipient shall
receive no more than one additional data
word)
t
RFS
75 70 60 60 60 50 Ready-to-final-STROBE time (no
STROBE edges shall be sent this long
after negation of DMARDY-)
t
RP
160 125 100 100 100 85 Ready-to-pause time (that recipient shall
wait to pause after negating DMARDY-)
t
IORDYZ
20 20 20 20 20 20 Maximum time before releasing IORDY
t
ZIORDY
0 0 0 0 0 0 Minimum time before driving STROBE
(see note 5)
t
ACK
20 20 20 20 20 20 Setup and hold times for DMACK-before
assertion or negation).
t
SS
50 50 50 50 50 50 Time from STROBE edge to negation of
DMARQ or assertion of STOP (when
sender terminates a burst)