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DISK DRIVE OPERATION
SpinPoint V40
Product Manual
28
5.2.2.1 The Host Interface Control Block
The SID2001 AT Controller provides an ATA interface to the host computer and can attach to an ATA-1,
2,3,4 or ATA-5 host. It provides a means for the host to access the Task File registers used to control the
transfer of data between host memory and the disk.
The Host Interface Control block can be programmed to execute various host read/write commands either
completely automatically without any DSP intervention, semi-automatically with minimal DSP intervention,
or manually with the aid of the DSP.
Of particular interest to most designers are the significant advances in ATA automation, which have been
incorporated into the AT controller of SID2001. The highlights of ATA automation are:
• Automatic data transfer management for multi-sector Read/Write commands without DSP intervention.
• Automatic data transfer management for Read/Write Multiple commands without DSP intervention.
• Automatic execution of read commands (Auto-Read command execution) for cached data in the buffer
by matching the first sector.
• Auto-Write command execution (first sector of a multiple sector write operation is automated, or the
transfer of one sector of the selected single sector write operation is automated).
• Automatic Task File registers updates during automatic multi-sector transfers.
• Programmable methods of IRQ assertion allow automation to work with different BIOS implementations
and different device drivers.
• Capability to execute multiple consecutive Auto-Write commands without loss of data in the buffer.
• 96-byte host FIFO to allow automation to occur smoothly during discontinuities in transfers on the ATA
interface.
• Ability to pause the ATA automatic transfers between the host and buffer on sector and block boundaries.
• Automation of an extensive portion of the ATA command set.
The SID2001 also supports a basic ATAPI reset command.
The SID2001 supports both PIO and DMA type transfers. The supported DMA type transfers include multi-
word, and synchronous DMA transfers. DMA transfers and PIO transfers utilize the bus in 8- or 16-bit mode,
depending upon the command being executed. The bus is automatically switched between 16- and 8-bit
mode while performing Read Long and Write Long commands at the time of ECC byte transfers.
Additional functionality is provided in the Host Interface Control block by the following features:
• Programmable transfer length for automatic ECC byte transfer on the AT bus.
• Automatically inserted wait states are provided to support the IOCHRDY signal pin functions at any
ATA interface speed.