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Preface
x Copyright © 2006 ARM Limited. All rights reserved. ARM DDI 0389B
About this manual
This is the Technical Reference Manual (TRM) for the PrimeCell AHB SRAM/NOR
Memory Controller.
Product revision status
The rnpn identifier indicates the revision status of the product described in this manual,
where:
rn Identifies the major revision of the product.
pn Identifies the minor revision or modification status of the product.
Intended audience
This manual is written for system designers, system integrators, and verification
engineers who are designing a System-on-Chip (SoC) device that uses the AHB MC.
The manual describes the external functionality of the AHB MC.
Using this manual
This manual is organized into the following chapters:
Chapter 1 Introduction
Read this chapter for a high-level view of the AHB MC and a description
of its features.
Chapter 2 Functional Overview
Read this chapter for a description of the major components of the AHB
MC and how they operate.
Chapter 3 Programmer’s Model
Read this chapter for a description of the AHB MC registers.
Chapter 4 Programmer’s Model for Test
Read this chapter for a description of the additional logic for integration
testing.
Chapter 5 Device Driver Requirements
Read this chapter for a description of device driver requirements for the
Static Memory Controller (SMC).