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SCPA033
12 PCI1520 Implementation Guide
Latency Timer Register (PCI offset 0Dh) – This register indicates the number of PCI clocks
the PCI1520 will be allowed access to the PCI bus if another master has its REQ# asserted.
The recommended value is 40h. However, the value should be dependent on the system
implementation and which devices need priority.
CardBus Latency Timer Register (PCI offset 1Bh) – This register indicates the number of
CardBus clocks the PCI1520 will be allowed access on the CardBus interface. Because the
CardBus interface is a point-to-point interface, the PCI1520 does not deassert CGNT# until a
transaction is finished. Therefore, this register has little effect on the system.
Subsystem Vendor ID and Subsystem ID Registers (PCI offsets 40h and 42h) –These
registers are used for subsystem and option card identification purposes. Typically, these
registers contain the OEM vendor ID and an OEM identified designator. These fields can be
programmed using the EEPROM or BIOS. If using BIOS, the SUBSYSRW bit (System Control
register, bit 5) must be cleared to 0. The SSVID and SSID registers can now be written. The
SUBSYSRW bit should be set to 1 after the registers are written.
8.2.2 PCI Configuration Registers (TI Extension)
System Control Register (PCI offset 80h) – This register contains many important system
dependent variables. Please refer to the datasheet for more details. Of possible interest to the
BIOS programmer: SER_STEP, INTRTIE, P2CCLK, MRBURSTDN, MRBURSTUP, and RIMUX.
Multifunction Routing Register (PCI offset 8Ch) – This register controls the seven
multifunction terminals of the PCI1520. This register must be set before the interrupt mode is
programmed in the Device Control register (PCI offset 92h).
Card Control Register (PCI offset 91h) – This register contains enable bits for RI_OUT# and
SPKROUT.
Device Control Register (PCI offset 92h) – This register contains the interrupt mode bits.
Power Management Capabilities Register (PCI offset A2h) – This register is important for
systems needing to wake from the D3 power state. Bit 15 reflects whether or not PME# is
supported from D3cold. Bit 4 is tied to bit 15 indicating that if PME# is supported from D3cold,
the system must be providing auxiliary power.
Power Management Control and Status Register (PCI offset A4h) – This register contains
the PME# enable bit (bit 8).
8.2.3 ExCA Compatibility Registers
ExCA Interrupt and General-Control Register (ExCA offset 03/43h) –Thisregisterisusedto
route CSTSCHG interrupts via PCI interrupts.
8.2.4 CardBus Socket Registers
Socket Control Register and Socket Power Management Register (CB offsets 10h and
20h) – These registers can be used to characterize how CB CLKRUN# functions.