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SCPA033
14 PCI1520 Implementation Guide
9.1.1 GRST# Only Registers
Global reset places all registers in their default state regardless of the state of the PME enable
bit. The GRST# signal is gated only by the SUSPEND# signal. This means that assertion of
SUSPEND# blocks the GRST# signal internally, thus preserving all register contents. The
registers cleared only by GRST# are:
• Status register (PCI offset 06h): bits 15-11, 8
• Secondary status register (PCI offset 16h): bits 15-11, 8
• Interrupt pin register (PCI offset 3Dh): bits 1,0 (function 1 only)
• Subsystem vendor ID register (PCI offset 40h): bits 15-0
• Subsystem ID register (PCI offset 42h): bits 15-0
• PC Card 16-bit legacy mode base address register (PCI offset 44h): bits 31-1
• System control register (PCI offset 80h): bits 31-29, 27-13, 11, 6-0
• Multifunction routing register (PCI offset 8Ch): bits 27-0
• Retry status register (PCI offset 90h): bits 7-5, 3, 1
• Card control register (PCI offset 91h): bits 7-5, 2-0
• Device control register (PCI offset 92h): bits 7-5, 3-0
• Diagnostic register (PCI offset 93h): bits 7-0
• Power management capabilities register (PCI offset A2h): bit 15
• General-purpose event status register (PCI offset A8h): bits 15-14
• General-purpose event enable register (PCI offset AAh): bits 15-14, 11, 8, 4-0
• General-purpose output (PCI offset AEh): bits 4-0
• Serial bus data (PCI offset B0h): bits 7-0
• Serial bus index (PCI offset B1h): bits 7-0
• Serial bus slave address register (PCI offset B2h): bits 7-0
• Serial bus control and status register (PCI offset B3h): bits 7, 5-0
• ExCA identification and revision register (ExCA offset 00h): bits 7-0
• ExCA global control register (ExCA offset 1Eh): bits 2-0
• Socket present state register (CardBus offset 08h): bit 29
• Socket power management register (CardBus offset 20h): bits 25-24