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SCPA033
PCI1520 Implementation Guide 21
12.2 Configuration Register Changes
• The device ID for the PCI1420 is AC51.
• The PCI1420 is both Intel 82365SL-DF and 82365SL register compatible. The PCI1225
is only 82365SL-DF register compatible. Bit 2 in the System Control register (PCI offset
80h) is now ExCA Power instead of reserved to allow for SL compatibility. The ExCA
Power Control register (ExCA offset 02h) also changes in SL mode.
• Bit 23 in the System Control register (PCI offset 80h) is now used to allow the PCI1420
to report as compliant to either revision 1.0 or 1.1 of the PCI Bus Power Management
Specification. In the PCI1225, this bit is reserved.
• Some of the values of the Multifunction Routing register (PCI offset 8Ch) matrix have
changed. When MFUNC5 = 1001b, it is now reserved instead of IRQ9. When MFUNC4
= 1111b, it is now reserved instead of IRQ15. When MFUNC2 = 1011b, it is now
reserved instead of IRQ11.
• Bit 7 in the Device Control register (PCI offset 92h) is now SKTPWR_LOCK instead of
RSVD. This bit, when set to ‘1b’, stops software from powering down the PC Card
socket while in the D3 power state. This may be necessary for wake on LAN.
• Bit 6 in the Diagnostic register (PCI offset 93h) is now AOSPMEN which disables the
oscillator power management features. This bit is reserved in the PCI1225.
• Bit 14 in the Power Management Capabilities register (PCI offset A2h) is now read/write
with a default of 1 indicating the PCI1420 supports PME# from D3cold when Vaux is
provided. This bit is read-only zero in the PCI1225.
12.3 Other Functional Differences
• The PCI1420 and PCI1225 are both natively supported by Windows XP, Windows 2000,
Windows ME, and Windows 98SE.