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PCI1520 Implementation Guide 17
11 Migration to the PCI1520 from the PCI1420
The major differences between the PCI1520 and PCI1420 are pinout, lower power consumption,
and lower cost. The pinout is changed on the PCI1520 in order to incorporate an internal
voltage regulator which allows the core to operate at 2.5V. When moving from the PCI1225 to
the PCI1520, please see Section 13 for the differences between the PCI1225 and PCI1420 in
addition to the changes from this section.
11.1 Hardware and Pin Assignment Changes
• The pinout on the PCI1520 is significantly changed from the PCI1420. This requires a
PCB redesign.
• A low dropout voltage regulator is integrated into the PCI1520 to supply 2.5V core
voltage. A voltage regulator enable pin (VR_EN#) has been added in place of one of the
VCCP pins. A core voltage input/output (VRPORT) pin has been added in place of the
VCCI pin. This pin is used to either input core voltage or allow for an external 1.0µF
bypass capacitor depending on the value of VR_EN#. A typical implementation would
enable the regulator by grounding VR_EN# and adding the bypass capacitor from
VRPORT to ground. For further details, see the datasheet.
• The PCI1520 does not have a VCCI pin. Signals clamped to VCCI on the PCI1420 are
clamped to VCCP on the PCI1520.
• A new power switch has been introduced for dual socket CardBus controllers. The
TPS2226A is recommended for new designs although the TPS2216 and TPS2206 are
still compatible with the PCI1520. All three power switches have very similar functionality
and can be designed onto the same footprint.
• The PCI1520 has integrated pullup resistors on the two CCLKRUN#//WP(IOIS16#)
terminals. All necessary pullup resistors on the PC Card interface have been integrated
in the PCI1520.
• A switchable pullup/pulldown resistor has been implemented on the two
CSTSCHG//BVD1(STSCHG#/RI#) terminals. The pullup is active when the 16BITCARD
bit (bit 4 in the Socket Present State register) is ‘1’, otherwise the pulldown resistor is
activated. This prevents unexpected PME# assertion.