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SCPA033
PCI1520 Implementation Guide 13
9 Power Management Considerations
9.1 D3 Wake Information
A power management event (PME) is the process by which a PCI or CardBus function can
request a change of its current power consumption state. Typically, a device uses PME# to
request a change from a power savings state to the fully operational state, D0. PME Context is
defined as the functional state information and logic required to generate PMEs, report PME
status, and enable PMEs. PCI Function Context refers to the small amounts of information held
internal to the function. This includes not only the contents of the function’s PCI registers, but
also information about the operation states of the function including state machine context and
other internal mechanisms.
When global reset (GRST#) is asserted, the PCI1520 is completely non-functional and is in a
default state. Output buffers are tristated and internal registers are reset. The result of PCI
reset (PRST#) being asserted is dependent on whether PME# is enabled or not. When PRST#
is asserted with neither function enabled for PME#, it causes the PCI1520 to tristate all output
buffers and reset all internal registers except for those considered ‘GRST# Only Registers’. If
PME# is enabled for either socket, the PCI1520 will maintain its ‘PME# Context Registers’.
According to the PCI Bus Power Management Interface Specification for PCI to CardBus
Bridges, a device returning to D0 from D3hot is required to assert an internal reset. The PCI
reset may or may not be asserted by the system. However, for a device returning to D0 from
D3cold however, PRST# must be asserted by the system.
For a wake from D3cold, the device needs to save its PME# context in order for software to
determine the source of the wake-up event. This is accomplished using PME# enable and
saving the PME# context registers. However, the device must also maintain certain registers
that are normally configured by BIOS at boot time. This is accomplished using GRST# and the
‘GRST# Only Registers.’ This allows a system to be in a low power state and resumed quickly
without needing BIOS to reprogram the device.
The sequence of events at power up are that GRST# and PRST# should be asserted. 100 µs
after PCLK is stable, GRST# can be deasserted. PRST# can be deasserted at the same time
as GRST# or any time there after. At this point, GRST# will stay deasserted until the system
completely cycles power and reboots. Now the system can put the PCI1520 into a lower power
state and may or may not assert PRST#.
The PCI1520 does not require a PCI clock to generate a PME# signal. However, it does require
a voltage source such as Vaux to be supplied and the pullup on PME# must also be connected
to Vaux. In addition, the VCCP pins and power switch must also have power in order to wake
from a card. Vaux is limited to 200mA for each socket.
For systems not implementing wake from D3, GRST# can be tied to PRST#.