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2.10ResetConsiderations
2.10.1SoftwareResetConsiderations
2.10.2HardwareResetConsiderations
2.11InterruptSupport
2.11.1InterruptEventsandRequests
PeripheralArchitecture
Peripheralclockandresetcontrolisdonethroughthepowerandsleepcontroller(PSC)modulethatis
includedwiththedevice.Formoreinformation,seeSection2.13.Additionally,thereisasoftwarereset
(theresetbitintheVLYNQcontrolregister,CTRL)withintheperipheralitself.Writinga1totheresetbit
resetsalloftheinternalstatemachinesoftheVLYNQmodule,theserialinterfaceisdisabled,andthelink
islost.TheVLYNQmoduleremainsinresetuntilthesoftwareclearsthebit.
Note:Whensettingtheresetbit,theVLYNQstatusregister(STAT)valueistheonlyvaluethatis
settothedefaultvalue.AlloftheotherVLYNQmemory-mappedregistersretaintheirvalues
priortothesoftwarereset.
Whenahardwareresetoccurs,theVLYNQperipheralresetsitsregistervaluestothedefaultvaluesand
theserialinterfaceisdisabled.Afterahardwarereset,theVLYNQmemorymappedregistersandany
chip-levelregistersthatareassociatedwithVLYNQ(forexample,pinmultiplexingregisters)mustbe
configuredappropriatelybeforedatatransmissioncanresume.
CAUTION
BecautiouswhenonlyresettingoneoftheVLYNQdevicesaftertwoormore
VLYNQdeviceshaveestablishedalink.IfonlyoneoftheVLYNQdevicesisin
reset,thennodataactivitycanoccuracrosstheserialinterfaceduringthetime
ofreset.
TheVLYNQmoduleinterruptVLQINTismappedtotheinterruptcontroller(INT55).Formoreinformation
ontheinterruptcontroller,seethedevice-specificdatamanual.
InterruptsgeneratewhenbitsaresetintheVLYNQinterruptpending/setregister(INTPENDSET).Bitsare
setintheINTPENDSETregisterwhenanyofthefollowingoccur:
•WritingdirectlytotheINTPENDSET
•Remoteinterrupt(viatheserialinterruptpacket)
•Serialbuserror
WhenINTPENDSETisanon-zerovalue,themethodofforwardingtheinterruptstatusdependsonthe
stateoftheINTLOCALbitintheVLYNQcontrolregister(CTRL):
•WhenINTLOCAL=0,thecontentsofINTPENDSETareinsertedintoaninterruptpacketandsent
overtheserialinterface.Whenpackettransmissioncompletes,theassociatedbitsclearin
INTPENDSET.
•WhenINTLOCAL=1,bitsinINTPENDSETtransfertotheVLYNQinterruptstatus/clearregister
(INTSTATCLR).Thelogical-ORofallofthebitsinINTSTATCLRisdrivenontotheinterruptline,
causingtheVLYNQINTtopulse.IfthesystemwritestoINTSTATCLRwhileinterruptsarestillpending,
anewVLQINTinterruptisgenerated.
20VLYNQPortSPRU938B–September2007
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