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3.2ControlRegister(CTRL)
VLYNQPortRegisters
Thecontrolregister(CTRL)determinesoperationoftheVLYNQmodule.TheCTRLisshowninFigure10
anddescribedinTable7.
Figure10.ControlRegister(CTRL)
31302927262423222120191816
PMENSCLKPUDISReservedRXSAMPELVALRTMVALIDWRRTMENABLETXFASTPATHReservedCLKDIV
R/W-0R/W-0R-0R/W-3hR/W-0R/W-0R/W-0R-0R/W-0
151413128763210
CLKDIRINTLOCALINTENABLEINTVECINT2CFGReservedAOPTDISABLEILOOPRESET
R/W-0R/W-0R/W-0R/W-0R/W-0R-0R/W-0R/W-0R/W-0
LEGEND:R/W=Read/Write;R=Readonly;-n=valueafterreset
Table7.ControlRegister(CTRL)FieldDescriptions
BitFieldValueDescription
31PMENPowermanagementenable.
0VLYNQCLKisalwaysactiveifitissetasanoutput(assumingthatVLYNQmoduleisenabled).
Ifsetasanoutput,VLYNQCLKbecomesinactivewhenthereisnotrafficovertheserialbus.
1
ThePMENbitshouldonlybesetto1whentheSCRUNisconnectedtotheremote/external
VLYNQdevice.
30SCLKPUDIS0Serialclockpull-updisable.Alwayswrite0.
29-27Reserved0Reserved.Alwaysreadas0.Writeshavenoeffect.
26-24RXSAMPELVAL0-7hRTMsamplevalue.IftheRTMENABLEbitis0,thereceivetimingmanagerforcesthevalueinthe
RXSAMPELVALbitastheclocksamplevalue.IftheRTMENABLEbitis1,thenthevaluesetby
theRXSAMPELVALbitisignored.Inordertomodifythevalue,youmustsimultaneouslywritea1
totheRTMVALIDWRbit.
23RTMVALIDWRRTMvalidwritebit.
0WillnotallowwritestoRXSAMPLEVALbits.
1WillallowwritestoRXSAMPLEVALbits.
22RTMENABLERTMenablebit.
ThereceivetimingmanagerusesthevaluesetintheRXSAMPLEVALbitastheclocksample
0
value.
1Thereceivetimingmanagerisenabled.Itautomaticallyselectsthereceiveclock.
21TXFASTPATH0-1Transmitfastpath.Whenset,thefastestpathischosenfortheserialdata.
20-19Reserved0Reserved.Alwaysreadas0.Writeshavenoeffect.
18-16CLKDIV0-7hSerialclockoutputdivider.
15CLKDIRSerialCLKdirection.DetermineswhethertheVLYNQCLKisaninputoranoutput.
0TheVLYNQCLKisexternallysourced.
TheVLYNQCLKisinternallysourcedandequaltotheVLYNQmodulesystemclockdividedbythe
1
dividervaluesetintheCLKDIVbit.
14INTLOCALInterruptlocal.
0TheinterruptisforwardedtotheremoteVLYNQdeviceovertheserialinterfaceasaninterrupt
packet.
Interruptispostedintheinterruptstatus/clearregisterandresultsintheassertionoftheVLQINTto
1
thedeviceinterruptcontrollers.
13INTENABLEInterruptenable.
0VLYNQmodulestatusinterruptsareignored.
VLYNQmodulestatusinterrupts(ifRERRORorLERRORbitsareset)arepostedtotheinterrupt
1
pending/setregister.
12-8INTVEC0-1FhInterruptvector.Thisbitindicateswhichbitintheinterruptpending/setregisterissetforVLYNQ
modulestatus(RERROR/LERROR)interrupts.
26VLYNQPortSPRU938B–September2007
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