Texas Instruments SPRU938B Network Card User Manual


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VLYNQinterrupt
pending/setregister
(INTPENDSET)
VLYNQ
Status/clear
register
(INTSTATCLR)
OR
Transmitserial
interruptpacket
VLQINT
(INT55)
14 0
INTLOCAL
VLYNQcontrolregister(CTRL)
Serialbuserror
(LERROR/RERROR)
CPUwrites
Serialinterrupt
packetfrom
remotedevice
INTLOCAL=1
INTLOCAL=0
2.11.2WritestoInterruptPending/SetRegister
PeripheralArchitecture
Foradditionalflexibilityofinterrupthandling,theINSTATbitintheinterruptpriorityvectorstatus/clear
register(INTPRI)reportsthehighestpriorityinterruptassertedinINTPENDSETwhenINTLOCAL=1in
CTRL.TheVLYNQinterpretsbit0oftheINSTATbitsasthehighestpriorityandinterpretsbit31asthe
lowestpriority.Thevaluethatisreturnedwhenreadisthevectorofthehighestpriorityinterrupt.Software
canclearthatinterruptbywritingbackthevectorvalue.Additionally,INTRPRIprovidesaread-onlystatus
bit(NOINTPEND)toindicatewhetherornotthereareanypendinginterruptsinINTSTATCLR.
TheVLYNQinterruptgenerationmechanismisshowninFigure8.
Figure8.InterruptGenerationMechanismBlockDiagram
Aspreviouslydiscussed,iftheCPUwritestotheVLYNQinterruptpending/setregister(INTPENDSET),
thendependingonthevalueoftheINTLOCALbitintheVLYNQcontrolregister(CTRL),thiswillresultin
alocalinterrupt(tothedeviceinterruptcontroller)oraninterruptpackettransmittedovertheserial
interfacetotheremotedevice.
SPRU938B–September2007VLYNQPort21
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