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2.11.3RemoteInterrupts
2.11.4SerialBusErrorInterrupts
2.12EDMAEventSupport
PeripheralArchitecture
Remoteinterruptsoccurwhenaninterruptpacketisreceivedovertheserialinterfacefromaremote
device.Theinterruptstatusisextractedfromthepacketandwrittentoalocationpointedtobythe
interruptpointerregister(INTPTR).
TheINTPTRshouldcontaintheaddressoftheinterruptpending/setregister(INTPENDSET).Toget
INTPTRtocontaintheaddressofINTPENDSET,programINTPTRwithavalueof14h(theoffsetfor
INTPENDSET).Additionally,theINT2CFGbitintheVLYNQcontrolregister(CTRL)mustbesetto1,
dictatingthattheVLYNQwritestoalocalregisterspace(inthiscase,INTPENDSET).
Onceaninterruptpacketisreceivedovertheserialinterface,theinterruptstatusisextractedandwritten
toINTPENDSET.AftertheinterruptstatusisextractedandwrittentoINTPENDSET,theinterrupt
generationoccursaspreviouslydescribedinSection2.11.2.
Thefollowingsummarizesthestepsthatarerequiredtoensurethatthedevicereceivestheremote
interrupts:
•ProgramtheVLYNQinterruptpointerregister(INTRPTR)withavalueof14h,whichistheoffset
addressoftheVLYNQinterrupt/pendingsetregister(INTPENDSET).
•SettheINT2CFGbitto1intheVLYNQcontrolregister(CTRL).
Duetoerroneoustransmitpacketsthataredetectedbyremotedevices(remoteerror)orerrorsinthe
inboundpackets(localerror),theserialbuserrorsresultinthesettingoftheRERRORorLERRORbitsin
theVLYNQstatusregister(STAT).
Additionally,iftheINTENABLEbitissetintheVLYNQcontrolregister(CTRL),settingtheRERRORor
LERRORbitscausethesestatusinterruptstoposttotheinterruptpending/setregister(INTPENDSET),
causingtheVLYNQINTtobeassertedtotheCPU.
Toensurethatserialbuserrorsresultininterruptstonotifytheapplicationsoftware,youmustperformthe
followingsteps:
1.SettheINTENABLEbitto1intheVLYNQcontrolregister(CTRL).
2.SettheINTVECbitsinCTRLtopointtoafreebitintheVLYNQinterruptpending/setregister
(INTPENDSET).TheserialbuserrorshouldresultinsettingthebitsinINTPENDSETthatarenotused
bytheapplicationsoftwareforotherinterrupts(bitlocationswrittendirectlyinINTPENDSETorvia
remoteinterrupts).
3.DuringVLYNQinitialization,theRERRORbitissetaftertheVLYNQmoduleachievesalink.Whenthe
linkbitissetintheVLYNQstatusregister(STAT),writea1totheRERRORbit.Writinga1tothe
RERRORbitclearstheRERRORbitandpreventsthesoftwareinterrupthandlerfromseeingthefirst
RERRORasalegitimateserialbuserrorinterrupt.
TheVLYNQmoduleontheDM643xdeviceisclassifiedasamasterperipheral.Classificationasamaster
peripheralnormallyimpliesthattheperipheralisabletosustainitsowntransferswithoutrelyingonany
externalperipherals(forexample,thesystemDMA,etc).However,theVLYNQmoduledoesnothavean
internalDMA(assomeothermasterperipherals).
Therefore,itislikelythattheVLYNQmodulecanrelyontheon-chipenhancedDMA(EDMA3)controller
forperformingbursttransfer.TheEDMA3canstillbeusedtoperformbursttransfersouttoremote
VLYNQmemorymap(writes).Thisusemodelprovidesbetterthroughputwithlessoverhead.
Note:ThereisnoVLYNQeventthatallowshardwaresynchronizationtooccurwiththeEDMA3
controllerontheDM643xdevice.
TheVLYNQmoduleusesa16-worddeepFIFOtobuffertheburstwrites.SincetheEDMA3controlleris
muchfastercomparedtotheserialVLYNQinterface,adataback-upcanoccur.Therefore,configuring
EDMA3foroptimaltransfersize,etc.isessential.
VLYNQPort 22SPRU938B–September2007
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