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VLYNQPortRegisters
Table8.StatusRegister(STAT)FieldDescriptions(continued)
BitFieldValueDescription
8RERRORRemoteError.Writea1tothisbittoclearit.
0Noerror
ThisbitindicatesthatadownstreamVLYNQmodulehasdetectedapacketerror.Thisbitis
1
setwhenanerrorindication,/E/,isreceivedfromtheserialinterface.SeeAppendixA.
Ifthisbitisset,andtheINTENABLE(bit13inVLYNQcontrolregister)isalsoset,itasserts
theVLYNQinterrupt(VLQINT).
7LERRORLocalerror.Writea1tothisbittoclearit.
0Noerror.
Thisbitindicatesthataninboundpacketcontainsanerrorthatisdetectedbythelocal
1
VLYNQmodule.
Ifthisbitisset,andtheINTENABLE(bit13inVLYNQcontrolregister)isalsoset,itasserts
theVLYNQinterrupt(VLQINT).
6NFEMPTY3FIFO3isnotempty.
0IndicatesthattheslavecommandFIFOisempty.
1IndicatesthattheslavecommandFIFOisnotempty.
5NFEMPTY2FIFO2isnotempty.
0IndicatesthattheslavedataFIFOisempty.
1IndicatesthattheslavedataFIFOisnotempty.
4NFEMPTY1FIFO1isnotempty.
0IndicatesthatthemastercommandFIFOisempty.
1IndicatesthatthemastercommandFIFOisnotempty.
3NFEMPTY0FIFO0isnotempty.
0IndicatesthatthemasterdataFIFOisempty.
1IndicatesthatthemasterdataFIFOisnotempty.
2SPENDPendingslaverequest.
0Nopendingslaverequests.
IndicatesdetectionofatransferrequestinitiatedbytheVLYNQmoduletotheoff-chip
1
peripheral(TXslaveconfigurationbusinterface).
1MPENDPendingmasterrequests.
0Nopendingmasterrequests.
Indicatesdetectionofatransferrequestinitiatedbyanoff-chipperipheraltotheVLYNQ
1
module(RXmasterconfigurationbusinterface).
0LINKLink
0Indicatesthattheserialinterfaceinitializationsequencehasnotyetcompletedorthelink
hastimedout.
1Indicatesthattheserialinterfaceinitializationsequencehascompletedsuccessfully.
SPRU938B–September2007VLYNQPort29
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