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Appendices Apx. C Pin Assignments
EQUIUM M40/M45/Sarellite M40/M45 Maintenance Manual C-15
AD10 /+VCC_CORE O J5 /+VCC_CORE O
AD11 DGND I J6 DGND I
AD12 /+VCC_CORE O K1 /H_RS#(1) O
AD13 DGND - K2 DGND -
AD14 /+VCC_CORE O K21 DGND O
AD15 DGND I K22 /+VCC_CORE I
AD16 /+VCC_CORE O K23 DGND O
AD17 DGND O K24 /H_DSTBN#1 O
AD18 /+VCC_CORE - K25 /H_D#(31) -
AD19 DGND I/O K26 DGND I/O
AD2 /H_A#(23) O K3 /H_HIT# O
Table C-22 CPU Socket (471-Pin) (5/9)
AD20 /H_DINV#3 - K4 /H_HITM# -
AD21 /H_D#(60) - K5 DGND O
AD22 DGND - K6 /+VCCP I
AD23 /H_D#(54) O L1 /H_BNR# O
AD24 /H_D#(57) I L2 /H_RS#(2) -
AD25 DGND O L21 /+VCCP O
AD26 /N$4169 - L22 DGND I
AD3 /H_A#(21) O L23 /H_D#(18) O
AD4 DGND I L24 /H_DSTBP#1 O
AD5 /H_A#(26) O L25 DGND I/O
AD6 /H_A#(28) - L26 /H_D#(26) O
AD7 DGND I/O L3 DGND -
AD8 /+VCC_CORE O L4 /H_DEFER# -
AD9 DGND - L5 /+VCCP -
AE1 /H_A#(30) O L6 DGND O