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Appendices Apx. C Pin Assignments
EQUIUM M40/M45/Sarellite M40/M45 Maintenance Manual C-27
137 DGND
-
138 DGND
-
139 /M_DATA(35)
I/O
140 /M_DATA(39)
I/O
141 /M_DATA(40)
I/O
142 /M_DATA(44)
I/O
143 /+V2.5
-
144 /+V2.5
-
145 /M_DATA(41)
I/O
146 /M_DATA(45)
I/O
147 /M_DQS(5)
O
148 /M_DM(5)
O
149 DGND
-
150 DGND
-
151 /M_DATA(42)
I/O
152 /M_DATA(46)
I/O
153 /M_DATA(43)
I/O
154 /M_DATA(47)
I/O
155 /+V2.5
-
156 /+V2.5
-
157 /+V2.5
-
158 /M_CLK_DDR0#
O
159 DGND
-
160 /M_CLK_DDR0
O
161 DGND
-
162 DGND
-
163 /M_DATA(48)
I/O
164 /M_DATA(52)
I/O
165 /M_DATA(49)
I/O
166 /M_DATA(53)
I/O
167 /+V2.5
-
168 /+V2.5
-
169 /M_DQS(6)
O
170 /M_DM(6)
O
171 /M_DATA(50)
I/O
172 /M_DATA(54)
I/O
173 DGND
-
174 DGND
-
175 /M_DATA(51)
I/O
176 /M_DATA(55)
I/O
177 /M_DATA(56)
I/O
178 /M_DATA(60)
I/O
179 /+V2.5
-
180 /+V2.5
-
181 /M_DATA(57)
I/O
182 /M_DATA(61)
I/O
Table C-25 DDR DIMM0 Socket (199-Pin) (4/4)
183 /M_DQS(7) O 184 /M_DM(7) O
185 DGND - 186 DGND -
187 /M_DATA(58) I/O 188 /M_DATA(62) I/O
Pin No. Signal Name I/O Pin No. Signal Name I/O