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Appendices Apx. C Pin Assignments
C-26 EQUIUM M40/M45/Sarellite M40/M45 Maintenance Manual
83 DGND
-
84 DGND
-
85 DGND
-
86 DGND
-
87 DGND
-
88 DGND
-
89 DGND
-
90 DGND
-
91 DGND
-
92 /+V2.5
-
93 /+V2.5
-
94 /+V2.5
-
95 /M_CKE1
O
96 /M_CKE0
O
97 DGND
I/O
98 DGND
-
99 /M_A(12)
I/O
100 /M_A(11)
I/O
101 /M_A(9)
I/O
102 /M_A(8)
I/O
103 DGND
-
104 DGND
-
105 /M_A(7)
I/O
106 /M_A(6)
I/O
107 /M_A(5)
I/O
108 /M_A(4)
I/O
109 /M_A(3)
I/O
110 /M_A(2)
I/O
111 /M_A(1)
I/O
112 /M_A(0)
I/O
113 /+V2.5
-
114 /+V2.5
-
115 /M_A(10)
I/O
116 /M_A(16)
O
117 /M_A(15)
O
118 /M_RAS#
O
119 /M_WE#
O
120 /M_CAS#
O
Table C-25 DDR DIMM0 Socket (199-Pin) (3/4)
121 /M_CS0#
O
122 /M_CS1#
O
123 /M_A(13)
-
124 DGND
-
125 DGND
-
126 DGND
-
127 /M_DATA(32)
I/O
128 /M_DATA(36)
I/O
129 /M_DATA(33)
I/O
130 /M_DATA(37)
I/O
131 /+V2.5
-
132 /+V2.5
-
133 /M_DQS(4)
O
134 /M_DM(4)
O
135 /M_DATA(34)
I/O
136 /M_DATA(38)
I/O