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Appendices Apx. C Pin Assignments
C-24 EQUIUM M40/M45/Sarellite M40/M45 Maintenance Manual
190 /M_DATA(63) I/O 191 /+V2.5 -
192 /+V2.5 - 193 /SB_SMDAT_3 I/O
194 /+V3S
-
195 /SB_SMCLK_3
I/O
196 DGND
-
197 /+V3S
-
198 DGND
-
199 DGND
-
C.25 CN508 DDR DIMM0 Socket (200-Pin)
Table C-25 DDR DIMM0 Socket (200-Pin)(1/4)
Pin No. Signal Name I/O Pin No. Signal Name I/O
1 /N$496545
O
2 /N$496545
-
3 DGND
-
4 DGND
-
5 /M_DATA(0)
I/O
6 /M_DATA(4)
I/O
7 /M_DATA(1)
I/O
8 /M_DATA(5)
I/O
9 /+V2.5
-
10 /+V2.5
-
11 /M_DQS(0)
O
12 /M_DM(0)
O
13 /M_DATA(2)
I/O
14 /M_DATA(6)
I/O
15 DGND
-
16 DGND
-
17 /M_DATA(3)
I/O
18 /M_DATA(7)
I/O
19 /M_DATA(8)
I/O
20 /M_DATA(12)
I/O
21 /+V2.5
-
22 /+V2.5
-
23 /M_DATA(9)
I/O
24 /M_DATA(13)
I/O
25 /M_DQS(1)
O
26 /M_DM(1)
O
27 DGND
-
28 DGND
-