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Appendices Apx. C Pin Assignments
EQUIUM M40/M45/Sarellite M40/M45 Maintenance Manual C-25
29 /M_DATA(10)
I/O
30 /M_DATA(14)
I/O
31 /M_DATA(11)
I/O
32 /M_DATA(15)
I/O
33 /+V2.5
-
34 /+V2.5
-
35 /M_CLK_DDR1
O
36 /+V2.5
-
37 /M_CLK_DDR1#
O
38 DGND
-
39 DGND
-
40 DGND
-
41 /M_DATA(16)
I/O
42 /M_DATA(20)
I/O
43 /M_DATA(17)
I/O
44 /M_DATA(21)
I/O
45 /+V2.5
-
46 /+V2.5
-
47 /M_DQS(2)
O
48 /M_DM(2)
O
49 /M_DATA(18)
I/O
50 /M_DATA(22)
I/O
51 DGND
-
52 DGND
-
53 /M_DATA(19)
I/O
54 /M_DATA(23)
I/O
55 /M_DATA(24)
I/O
56 /M_DATA(28)
I/O
57 /+V2.5
-
58 /+V2.5
-
Table C-25 DDR DIMM0 Socket (199-Pin) (2/4)
59 /M_DATA(25)
I/O
60 /M_DATA(29)
I/O
61 /M_DQS(3)
O
62 /M_DM(3)
O
63 DGND
-
64 DGND
-
65 /M_DATA(26)
I/O
66 /M_DATA(30)
I/O
67 /M_DATA(27)
I/O
68 /M_DATA(31)
I/O
69 /+V2.5
-
70 /+V2.5
-
71 DGND
-
72 DGND
-
73 DGND
-
74 DGND
-
75 DGND
-
76 DGND
-
77 DGND
-
78 DGND
-
79 DGND
-
80 DGND
-
81 /+V2.5
-
82 /+V2.5
-