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Toshiba Corporation Digital Media Network Company
Page 8 of 153
© 2003, Copyright TOSHIBA Corporation All Rights Reserved
10.4 HOST INTERFACE TIMING........................................................................................................................ 35
10.4.1
Program I/O Write Timing............................................................................................................. 35
10.4.2
Program I/O Read Timing.............................................................................................................. 36
10.4.3
Multiword DMA Write Timing ......................................................................................................37
10.4.4
Multiword DMA Read Timing .......................................................................................................38
10.4.5
Ultra DMA Timing ......................................................................................................................... 39
10.4.6
Reset Timing................................................................................................................................... 48
10.5 GROUNDING............................................................................................................................................. 48
10.6 ADDRESS DECODING................................................................................................................................49
10.7 REGISTER DESCRIPTION .......................................................................................................................... 50
10.7.1
Data Register .................................................................................................................................. 50
10.7.2
Error Register ................................................................................................................................. 51
10.7.3
Features Register (Write Precompensation Register) ................................................................. 51
10.7.4
Sector Count Register..................................................................................................................... 52
10.7.5
Sector Number Register................................................................................................................. 53
10.7.6
Cylinder Low Registers.................................................................................................................. 53
10.7.7
Cylinder High Registers................................................................................................................. 53
10.7.8
Device/Head Register ..................................................................................................................... 54
10.7.9
Status Register ............................................................................................................................... 55
10.7.10
Command Register...................................................................................................................... 56
10.7.11
Alternate Status Register........................................................................................................... 58
10.7.12
Device Control Register.............................................................................................................. 58
10.7.13
Device Address register.............................................................................................................. 58
10.8 COMMAND DESCRIPTIONS ....................................................................................................................... 60
10.8.1
Nop (00h) ...................................................................................................................................... 61
10.8.2
Recalibrate (1xh).......................................................................................................................... 61
10.8.3
Flush Cache (E7h)........................................................................................................................ 61
10.8.4
Flush Cache EXT (EAh) .............................................................................................................. 61
10.8.5
Read Sector (20h/21h).................................................................................................................. 62
10.8.6
Read Sector EXT (24h) ................................................................................................................ 62
10.8.7
Write Sector (30h/31h)................................................................................................................. 63
10.8.8
Write Sector EXT (34h) ............................................................................................................... 63
10.8.9
Read Verify (40h) ......................................................................................................................... 64
10.8.10
Read Verify EXT (42h)............................................................................................................. 64
10.8.11
Write Verify (3Ch).................................................................................................................... 65
10.8.12
Format Track (50h) ................................................................................................................ 65
10.8.13
Seek (7xh).................................................................................................................................. 66
10.8.14
Toshiba Specific........................................................................................................................... 66
10.8.15
Execute Diagnostics (90h)........................................................................................................ 67
10.8.16
Initialize Device Parameters (91h) ......................................................................................... 67
10.8.17
Download Microcode (92h).......................................................................................................68
10.8.18
Read Multiple (C4h)................................................................................................................. 69
10.8.19
Read Multiple EXT (29h)......................................................................................................... 70
10.8.20
Write Multiple (C5h)................................................................................................................ 70
10.8.21
Write Multiple EXT (39h)........................................................................................................ 72
10.8.22
Set Multiple Mode (C6h).......................................................................................................... 72
10.8.23
Read DMA (C8h/C9h)............................................................................................................... 73
10.8.24
Read DMA EXT (25h) .............................................................................................................. 73
10.8.25
Write DMA (CAh/CBh) ............................................................................................................74
10.8.26
Write DMA EXT (35h) ............................................................................................................. 74
10.8.27
Power Control (Exh)................................................................................................................. 75
10.8.28
Read Buffer (E4h)..................................................................................................................... 77
10.8.29
Write Buffer (E8h).................................................................................................................... 77
10.8.30
Identify Device (ECh)............................................................................................................... 77
10.8.31
SET MAX (F9h)........................................................................................................................... 91
10.8.32
SET MAX ADDRESS EXT (37h) ............................................................................................... 94
10.8.33
Read Native Max Address (F8h) ........................................................................................... 94
10.8.34
Read Native Max Address EXT (27h) ................................................................................... 95