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18 www.xilinx.com SP601 Hardware User Guide
UG518 (v1.1) August 19, 2009
Chapter 1: SP601 Evaluation Board
3. SPI x4 Flash
The Xilinx Spartan-6 FPGA hosts a SPI interface which is visible to the Xilinx iMPACT
configuration tool. The SPI memory device operates at 3.0V; the Spartan-6 FPGA I/Os are
3.3V tolerant and provide electrically compatible logic levels to directly access the SPI flash
through a 2.5V bank. The XC6SLX16-2CSG324 is a master device when accessing an
external SPI flash memory device.
The SP601 SPI interface has two parallel connected configuration options (see Figure 1-7):
an SPI X4 (Winbond W25Q64VSFIG) 64-Mb flash memory device and a flash
programming header (J12). J12 supports a user-defined SPI mezzanine board. The SPI
configuration source is selected via SPI select jumper J15. For details on configuring the
FPGA, see “Configuration Options.”
X-Ref Target - Figure 1-6
Figure 1-6: J12 SPI Flash Programming Header
FPGA_D1_MISO2
J12
1
2
3
4
5
6
7
8
9
FPGA_D2_MISO3
FPGA_PROG_B
FPGA_MOSI_CSI_B_MISO0
SPI_CS_B
FPGA_CCLK
FPGA_D0_DIN_MISO_MISO1
UG518_06_070809
GND
VCC3V3
Silkscreen
TMS
TDI
TDO
TCK
GND
3V3
HDR_1X9