Interlocked Memory Instructions (Alpha Only)
A.3 Noncompliant Code Characteristics
or in assembly language written in MACRO–32 or MACRO–64. In some
cases, a branch was introduced between the LDx_L and STx_C instructions.
This can be addressed by recompiling.
• Some code compiled with very old BLISS, MACRO–32, DEC Pascal, or DEC
COBOL compilers may contain noncompliant sequences. Early versions of
these compilers contained a code scheduling bug where a load was incorrectly
scheduled after a load_locked.
This can be addressed by recompiling.
• In rare cases, the MACRO–32 compiler may generate a noncompliant code
sequence for a BBSSI or BBCCI instruction where there are too few free
registers.
This can be addressed by recompiling.
• Errors may be generated by incorrectly coded MACRO–64 or MACRO–32 and
incorrectly coded assembly language embedded in C or C++ source using the
ASM function.
This requires source code changes. The new MACRO–32 compiler flags
noncompliant code at compile time.
If the SRM_CHECK tool finds a violation in an image, you should recompile the
image with the appropriate compiler (see Section A.5). After recompiling, you
should analyze the image again. If violations remain after recompiling, examine
the source code to determine why the code scheduling violation exists. Then
make the appropriate changes to the source code.
A.4 Coding Requirements
The Alpha Architecture Reference Manual describes how an atomic update of
data between processors must be formed. The Third Edition, in particular, has
much more information on this topic. This edition details the conventions of the
interlocked memory sequence.
Exceptions to the following two requirements are the source of all known
noncompliant code:
• There cannot be a memory operation (load or store) between the LDx_L (load
locked) and STx_C (store conditional) instructions in an interlocked sequence.
• There cannot be a branch taken between an LDx_L and an STx_C instruction.
Rather, execution must "fall through" from the LDx_L to the STx_C without
taking a branch.
Any branch whose target is between an LDx_L and matching STx_C creates
a noncompliant sequence. For instance, any branch to "label" in the following
example would result in noncompliant code, regardless of whether the branch
instruction itself was within or outside of the sequence:
LDx_L Rx, n(Ry)
...
label: ...
STx_C Rx, n(Ry)
Therefore, the SRM_CHECK tool looks for the following:
• Any memory operation (LDx/STx) between an LDx_L and an STx_C
• Any branch that has a destination between an LDx_L and an STx_C
Interlocked Memory Instructions (Alpha Only) A–3
