Filter
Top Products
CHAPTER II -4
1.3.2 ASIC
The ASIC is composed of a Cell Based IC that contains the following functional blocks.
(1) Oscillator circuit
Generates the main clock for the CPU by dividing the source clock frequency by two.
(2) Address Generator
Generates the address bus by latching the AD bus with the ALE signal.
(3) Address decoder
Generates the CS signal for each device.
(4) DRAM control
Generates the RAS, CAS, WE, OE and MA signals for the DRAM and controls the
refresh processing (CAS before RAS self-refreshing method).
(5) Interrupt control
Interrupt levels:
Priority High 9 TIMER 3 (Watch Dog)
8 MONITOR
7 FIFO
6 EXINT
5 TIMER 1
4BD
3 SPARE
2 CDCC / BOISE / DATA EXTENTION
Low 1 TIMER 2
Note: All the interrupts can be masked.
(6) Timers
The following timers are included:
Timer 1 16-bit timer
Timer 2 10-bit timer
Timer 3 Watch-dog timer
(7) FIFO
A 10Kbit FIFO is included. Data for one raster is transferred from the RAM to the
FIFO by DMA transmission and is output as serial video data. The data cycle is
6.13mhz.