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CHAPTER II -5
(8) Parallel I/O
<Data receive Mode>
There are two modes in this unit. One is the CPU receive mode and the other is the
DMA receive mode. In the CPU receive mode the CPU receives the command data
from the PC, and after the CPU is switched to the DMA mode, it receives the image
data and writes it to the DRAM directly.
90 µsec
STROBE
BUSY
ACK
STROBE
BUSY
ACK
0.5 µsec
0.5 µsec1.5 µsec
CPU Receive Mode
DMA Receive Mode
BUSY goes HIGH at the falling edge of the STROBE signal. The data (8 bits) from
the PC is latched into the data buffer at the rising edge of the STROBE signal. The
pulse width of ACK varies according to the speed MODE as shown above. BUSY
goes LOW on the rising edge of ACK.
<IEEE1284 support>
This supports the IEEE1284 data transfer with the following mode.
Nibble mode
Byte mode
ECP mode
(9) Data extension
This circuit extents the compressed image data which are received from the PC, and
writes the bit map data to the FIFO.
(10) Software support
Supports 16 x 16 rotation, bit expansion, bit search, and decimal point conversion.
(11) EEPROM I/O
One output port and one I/O port are assigned.