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Integrated A.G.P. Compliant Target/66Mhz Host-to-PCI Bridge
– AGP v2.0 Compliant
– Supports Graphic Window Size from 4MBytes to 256MBytes
– Supports Pipelined Process in CPU-to-Integrated 3D A.G.P. VGA Access
– Supports 8 Way, 16 Entries Page Table Cache for GART to Enhance Integrated A.G.P. VGA
Controller Read/Write Performance
– Supports PCI-to-PCI Bridge Function for Memory Write from 33Mhz PCI Bus to Integrated
A.G.P. VGA
– Supports Additional AGP slot with 4X and Fast Write Transaction
Meet PC99 Requirements
PCI 2.2 Specification Compliant
High Performance PCI Arbiter
– Supports up to 4 PCI Masters
– Rotating Priority Arbitration Scheme
– Advanced Arbitration Scheme Minimizing Arbitration Overhead.
– Guaranteed Minimum Access Time for CPU And PCI Masters
Integrated Host-To-PCI Bridge
– Zero Wait State Burst Cycles
– CPU-to-PCI Pipeline Access
– 256B to 4KB PCI Burst Length for PCI Masters
– PCI Master Initiated Graphical Texture Write Cycles Re-mapping
– Reassembles PCI Burst Data Size into Optimized Block Size
Fast PCI IDE Master/Slave Controller
– Supports PCI Bus Mastering