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Chapter 4 System Support
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-2
4.2 PCI BUS OVERVIEW
NOTE: This section describes the PCI bus in general and highlights bus implementation
in this particular system. For detailed information regarding PCI bus operation, refer to
the PCI Local Bus Specification Revision 2.2.
This system implements a 32-bit Peripheral Component Interconnect (PCI) bus (spec. 2.2)
operating at 33 MHz. The PCI bus handles address/data transfers through the identification of
devices and functions on the bus. A device is typically defined as a component or slot that resides
on the PCI bus (although some components such as the MCH and ICH are organized as multiple
devices). A function is defined as the end source or target of the bus transaction. A device may
contain one or more functions.
In the standard configuration these systems use a hierarchy of three PCI buses (Figure 4-1). The
PCI bus #0 is internal to the MCH/ICH chipset components and is not physically accessible. The
AGP bus that services the AGP slot is designated as PCI bus #1. All PCI slots reside on PCI bus
#2.
Figure 4-1. PCI Bus Devices and Functions
Hub Link Bus
82850 MCH Component
AGP
Bridge
Function
Mem. Cntlr.
Function
PCI
Bus #0
82801BA ICH2 Component
PCI Bridge
Function
EIDE
Controller
Function
USB
I/F
Function
SMBus
Controller
Function
LPC
Bridge
Function
AC97
Audio
Function
PCI Bus #0
AGP Connector
PCI Bus #1
(AGP Bus)
Hub Link I/F
PCI
Bus #2
Hub Link I/F
NIC
I/F
Function
PCI Connector 1
PCI Connector 2
PCI Connector 3
PCI Connector 4
PCI Connector 5
Not used in these systems.
ES1373
Audio
Controller