Filter
Top Products
Chapter 4 System Support
Compaq Deskpro EXS and Workstation 300 Personal Computers
Featuring the Intel Pentium 4 Processor
First Edition - December 2000
4-10
4.3 AGP BUS OVERVIEW
NOTE: This section provides a brief description of AGP bus operation. For a detailed
description of AGP bus operations as supported by these systems refer to the AGP
Interface Specification Rev. 2.0 available at the following AGP forum web site:
http://www.agpforum.org/index.htm
The Accelerated Graphics Port (AGP) bus is specifically designed as an economical yet high-
performance interface for graphics adapters, especially those designed for 3D operations. The
AGP interface is designed to give graphics adapters dedicated pipelined access to system memory
for the purpose of off-loading texturing, z-buffering, and alpha blending used in 3D graphics
operations. By off-loading a large portion of 3D data to system memory the AGP graphics adapter
only requires enough memory for frame buffer (display image) refreshing.
4.3.1 BUS TRANSACTIONS
The operation of the AGP bus is based on the 66-MHz PCI specification but includes additional
mechanisms to increase bandwidth. During the configuration phase the AGP bus acts in
accordance with PCI protocol. Once graphics data handling operation is initiated, AGP-defined
protocols take effect. The AGP graphics adapter acts generally as the AGP master, but can also
behave as a “PCI” target during fast writes from the MCH.
Key differences between the AGP interface and the PCI interface are as follows:
♦ Address phase and associated data transfer phase are disconnected transactions. Addressing
and data transferring occur as contiguous actions on the PCI bus. On the AGP bus a request
for data and the transfer of data may be separated by other operations.
♦ Commands on the AGP bus specify system memory accesses only. Unlike the PCI bus,
commands involving I/O and configuration are not required or allowed. The system memory
address space used in AGP operations is the same linear space used by PCI memory space
commands, but is further specified by the graphics address re-mapping table (GART) of the
north bridge component.
♦ Data transactions on the AGP bus involve eight bytes or multiples of eight bytes. The AGP
memory addressing protocol uses 8-byte boundaries as opposed to PCI’s 4-byte boundaries. If
a transfer of less than eight bytes is needed, the remaining bytes are filled with arbitrary data
that is discarded by the target.
♦ Pipelined requests are defined by length or size on the AGP bus. The PCI bus defines transfer
lengths with the FRAME- signal.
There are two basic types of transactions on the AGP bus: data requests (addressing) and data
transfers. These actions are separate from each other.