Dell™ PowerEdge™ R610 Technical Guidebook
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Key features of the PowerEdge R610 memory system include:
•Registered(RDIMM)andUnbuered(UDIMM)ECCDDR3technology
•Eachchannelcarries64dataandeightECCbits
•Supportforupto96GBofRDIMMmemory(withtwelve8GBRDIMMs)
•Supportforupto24GBofUDIMMmemory(withtwelve2GBUDIMMs)
•Supportfor1066/1333MHzsingle-anddual-rankDIMMs
•Supportfor1066MHzquad-rankDIMMs
•SingleDIMMcongurationonlywithDIMMinsocketA1
•SupportODT(OnDieTermination)Clockgating(CKE)toconservepowerwhenDIMMsarenot
accessed
•DIMMsenteralowpowerself-refreshmode
•I2CaccesstoSPDEEPROMforaccesstoRDIMMthermalsensors
•SingleBitErrorCorrection
•SDDC(SingleDeviceDataCorrection–x4orx8devices)
•SupportforClosedLoop
•ThermalManagementonRDIMMsandUDIMMs
•MultiBitErrorDetectionSupportforMemoryOptimizedMode
•SupportforAdvancedECCmodeSupportforMemoryMirroring
B. DIMMs Supported
The DDR3 memory interface consists of three channels, with up to two RDIMMs or UDIMMs per chan-
nel for single-/dual-rank and up to two RDIMMs per channel for quad rank. The interface uses 2GB, 4GB,
or 8GB RDIMMs. 1GB or 2GB UDIMMs are also supported. The memory mode is dependent on how the
memory is populated in the system:
Three channels per CPU populated identically.
In a dual-processor configuration, the memory configurations for each processor must be identical
•Typically,thesystemwillbesettoruninMemoryOptimized(IndependentChannel)modein
this configuration. This mode oers the most DIMM population flexibility and system memory
capacity, but oers the least number of RAS (reliability, availability, service) features.
•MemorymodulesareinstalledinnumericorderforthesocketsbeginningwithA1orB1
•Allthreechannelsmustbepopulatedidentically.
•ThersttwochannelsperCPUpopulatedidenticallywiththethirdchannelunused
•Typically,twochannelsoperateinAdvancedECC(Lockstep)modewitheachotherby
having the cache line split across both channels. This mode provides improved RAS
features (SDDC support for x8-based memory).
•ForMemoryMirroring,twochannelsoperateasmirrorsofeachother—writesgoto
both channels and reads alternate between the two channels.
•ForMemoryMirroringorAdvancedECCMode,thethreesocketsfurthestfromtheprocessor
are unused and memory modules are installed beginning with socket A2 or B2 and proceeding
inthefollowingorder:A2,A3,A5,andA6
•OnechannelperCPUpopulated
•ThisisasimpleMemoryOptimizedmode.Mirroringisnotsupported.
The PowerEdge R610 memory interface supports memory demand and patrol scrubbing, single-bit
correction and multi-bit error detection. Correction of a x4 or x8 device failure is also possible with
SDDC in the Advanced ECC mode. Additionally, correction of a x4 device failure is possible in the
Memory Optimized mode.
•
If DIMMs of dierent speeds are mixed, all channels will operate at the fastest common frequency.
•RDIMMsandUDIMMscannotbemixed.
•Ifmemorymirroringisenabled,identicalDIMMsmustbeinstalledinthesameslotsacrossboth
channels. The third channel of each processor is unavailable for memory mirroring.
•
TherstDIMMslotineachchanneliscolor-codedwithwhiteejectiontabsforeaseofinstallation.