Dell R610 Server User Manual


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Dell™ PowerEdge™ R610 Technical Guidebook
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H. Optimizer (Independent Channel) Mode
In this mode, all three channels are populated with identical memory modules. This mode permits a
larger total memory capacity but does not support SDDC with x8-based memory modules.
A minimal single-channel configuration of 1GB memory modules per processor is also supported in
this mode.
SECTION 8. CHIPSET
A. Overview / Description
ThePowerEdgeR610planarincorporatedtheIntel5520chipset(codenamedTylersburg)forI/Oand
processorinterfacing.TylersburgisdesignedtosupportIntel's5500seriesprocessors(codenamed
Nehalem-EP),QPIinterconnect,DDR3memorytechnology,andPCIExpressGeneration2.The
Tylersburg chipset consists of the Tylersburg-36D IOH and ICH9.
The Intel 5520 chipset (code named Tylersburg) I/O Hub (IOH)
The planar uses the The Intel
®
5520chipset(codenamedTylersburg)I/OHub(IOH)-36DIOHtoprovide
alinkbetweenthe5500series2Sprocessor(NehalemEP)andI/Ocomponents.Themaincomponents
oftheIOHconsistoftwofull-widthQuickPathInterconnectlinks(onetoeachprocessor),36lanesof
PCI Express Gen2, a x4 Direct Media Interface (DMI), and an integrated IOxAPIC.
IOH QuickPath Interconnect (QPI)
TheQuickPathArchitectureconsistsofserialpoint-to-pointinterconnectsfortheprocessorsandthe
IOH.ThePowerEdgeR610hasatotalofthreeQuickPathInterconnect(QPI)links:onelinkconnecting
the processors and links connecting both processors with the IOH. Each link consists of 20 lanes
(full-width) in each direction with a link speed of up to 6.4 GT/s. An additional lane is reserved for a
forwardedclock.DataissentovertheQPIlinksaspackets.
TheQuickPathArchitectureimplementedintheIOHandCPUsfeaturesfourlayers.ThePhysicallayer
consists of the actual connection between components. It supports Polarity Inversion and Lane Reversal
for optimizing component placement and routing. The Link layer is responsible for flow control and the
reliabletransmissionofdata.TheRoutinglayerisresponsiblefortheroutingofQPIdatapackets.Finally,
the Protocol layer is responsible for high-level protocol communications, including the implementation of
a MESIF (Modify, Exclusive, Shared, Invalid, Forward) cache coherence protocol.
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