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20 p5-570 Technical Overview and Introduction
2.1 The POWER5 chip
The POWER5 chip features single-threaded and multi-threaded execution, providing higher
performance in the single-threaded mode than its POWER4 predecessor provides at
equivalent frequencies. POWER5 maintains both binary and architectural compatibility with
existing POWER4 systems to ensure that binaries continue executing properly and that all
application optimizations carry forward to newer systems. POWER5 provides additional
enhancements such as virtualization, improved reliability, availability, and serviceability at
both chip and system levels, and it has been designed to support speeds up to 3 GHz.
Figure 2-2 shows the high-level structures of POWER4 and POWER5 processor-based
systems. The POWER4 scales up to a 32-way symmetric multiprocessor. Going beyond
32 processors increases interprocessor communication, resulting in higher traffic on the
interconnection fabric bus. This can cause greater contention and negatively affect system
scalability.
Figure 2-2 POWER4 and POWER5 system structures
Moving the L3 cache provides significantly more cache on the processor side than was
available previously, thus reducing traffic on the fabric bus and enabling POWER5
processor-based systems to scale to higher levels of symmetric multiprocessing. The
POWER5 supports a 1.9 MB on-chip L2 cache, implemented as three identical slices with
separate controllers for each. Either processor core can independently access each L2
controller. The L3 cache, with a capacity of 36 MB, operates as a backdoor with separate
buses for reads and writes that operate at half processor speed.
Because of the higher transistor density of the POWER5 0.13-
µm technology, it was possible
to move the memory controller on-chip and eliminate a chip that was previously needed for
the memory controller function. These changes in the POWER5 processor also have the
significant side benefits of reducing latency to the L3 cache and main memory, as well as
reducing the number of chips that are necessary to build a system.
The POWER5 processor supports the 64-bit PowerPC® architecture. A single die contains
two identical processor cores, each supporting two logical threads. This architecture makes
the chip appear as a four-way symmetric multiprocessor to the operating system. The
POWER5 processor core has been designed to support both enhanced simultaneous
multi-threading (SMT) and single-threaded (ST) operation modes.
Processor Processor
L2
cache
Fabric
controller
L3
cache
Memory
controller
Memory
Processor Processor
L2
cache
Fabric
controller
L3
cache
Memory
controller
Memory
Processor Processor
L2
cache
Fabric
controller
L3
cache
Memory
controller
Memory
Processor Processor
L2
cache
Fabric
controller
L3
cache
Memory
controller
Memory
POWER4 POWER5
Fabric bus
Fabric bus
Fabric bus