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INTEL 186 EB/EC EVALUATION BOARD USER’S MANUAL
2-2
Figure 2-2. Intel 186 EC Evaluation Board Layout
TP4 TP3 TP2
80X186EC EVAL 3V / 5V
TP1
+5V GND
U6
J2
JP2
A5288-01
JP1
GNDGND
CLKOUTDT-R#
+5VDEN#
+12VRESOUT
GCS5#BHE#
NMIWR#
LOCK#RD#
ALELA19
READYLA18
HOLDLA17
HLDALA16
GNDGND
AD15LA15
AD14LA14
AD13LA13
AD12LA12
AD11LA11
AD10LA10
AD9LA9
AD8LA8
GNDGND
AD7LA7
AD6LA6
AD5LA5
AD4LA4
AD3LA3
AD2LA2
AD1LA1
AD0LA0
V
CC
V
CC
A B C
D
A
B
C
WRT PROT V
PP
SELECT
5V/3V Select
A B C
E2 D
C19
R2
TP7
DCE ConntectorPC Interface
P2
P1
TP5
R3
J1
C2 C3
U2
C8
C12C11
C10
E1
C
B
A
C21 R11
C22
C31
C20
C24
R12
R13
U11
C30
C32
C33
C25
C26
D3
D1
L2
L3
GND
RP1
GND
TP6
U5
U3
R7R8C13
L1
C5
C4
Y1
C9
U4
C6
S1
Q1
R4
R5
C7
R6
R1
C1U1
C14
U14
U12 U8
E3
C18
R10
C17
U10
E4
FLASH
PWRDN
A
B
C
E5
186/188
SELECT
C29
+12VGCS7#
+5VGCS6#
GNDGND
CTS1#DRQ3
P2.6DRQ2
TXD1DRQ1
RXD1DRQ0
P2.3GND
BCLK0INTA#
GNDINT7
WDTOUT#INT6
P3.5INT5
P3.4INT4
P3.3INT3
P3.2INT2
P3.1INT1
P3.0INT0
V
CC
V
CC
T0OUTT1IN
T1OUTT0IN
C27
U9
U13
C15
U7
C16
C34
C23C28
R9
GND
TP8