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INTEL 186 EB/EC EVALUATION BOARD USER’S MANUAL
3-14
Figure 3-8. CPU Bus Expansion (EB and EC)
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
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57
59
2 - V
CC
4 - D0 Bidirectional
6 - D1 Bidirectional
8 - D2 Bidirectional
10 - D3 Bidirectional
12 - D4 Bidirectional
14 - D5 Bidirectional
16 - D6 Bidirectional
18 - D7 Bidirectional
20 - V
SS
22 - D8 Bidirectional
24 - D9 Bidirectional
26 - D10 Bidirectional
28 - D11 Bidirectional
30 - D12 Bidirectional
32 - D13 Bidirectional
34 - D14 Bidirectional
36 - D15 Bidirectional
38 - V
SS
40 - HLDA
42 - HOLD
44 - READY Input
46 - ALE
48 - LOCK#
50 - NMI
52 - GCS5#
54 - +12 VDC
56 - +5 VDC
58 - CLKOUT
60 - V
SS
V
CC
..............................
LA0 Output..................
LA1 Output..................
LA2 Output..................
LA3 Output..................
LA4 Output..................
LA5 Output..................
LA6 Output..................
LA7 Output..................
V
SS
..............................
LA8 Output..................
LA9 Output.................
LA10 Output................
LA11 Output................
LA12 Output................
LA13 Output................
LA14 Output................
LA15 Output................
V
SS
...............................
LA16.............................
LA17............................
LA18...........................
LA19...........................
RD#............................
WR#............................
BHE#..........................
RESOUT.....................
DEN#...........................
DT-R#.........................
V
SS
..............................
JP1 Memory - I/O Expansion Connector
2x30 Pin Molex* 39-51-6004 or Equivalent