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PRELIMINARY 25
8XC251SA/SB/SP/SQ HIGH-PERFORMANCE CHMOS MICROCONTROLLER
5.3.2 EXTERNAL BUS CYCLES, PAGE MODE
Figure 10. External Bus Cycle: Code Fetch (Page Mode)
XTAL1
ALE
T
LHLL
†
A15:8 D7:0
T
RHDZ1
RD#/PSEN#
P2
P0/A16/A17
T
RHDX
T
LLRL
†
T
AVLL
†
T
RLDV
†
T
RLAZ
T
AVRL
†
T
AVDV1
†
T
AVDV2
†
T
OSC
A4213-02
T
LHAX
†
Instruction In
A7:0/A16/A17
D7:0
Instruction In
A7:0/A16/A17
Page Miss
††
Page Hit
††
T
AVDV3
†
The value of this parameter depends on wait states. See the table of AC characteristics.
††
A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one
state (2
T
OSC
); a page miss requires two states (4
T
OSC
).
†††
During a sequence of page hits, PSEN# remains low until the end of the last page-hit cycle.
T
LLAX
†††