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8.3 Plug and Play (PnP)
The system BIOS supports the following industry standards for making the system “Plug and Play ready”
such as ACPI, PCI local bus specification rev 2.1 and SMBIOS 1.
8.3.1 Resource Allocation
The system BIOS identifies, allocates, and initializes resources in a manner consistent with industry
standards. The BIOS scans, in order, for the following:
ISA devices: Add-in ISA devices are not supported on this platform. However, some standard
PC peripherals may require ISA-style resources – resources for these devices will be reserved as
needed.
Add-in video graphics adapter (VGA) devices: If found, the BIOS initializes and allocates resources to
these devices.
PCI Devices: The BIOS allocates resources according to the parameters set up by the SSU and as
required by the PCI Local Bus Specification, Revision 2.1.
The system BIOS Power-on Self Test (POST) guarantees that there are no resource conflicts prior to
booting the system. Please note that PCI device drivers are required to support the sharing of IRQs.
Sharing IRQs should not be considered a resource conflict. Note that only four legacy IRQs are available
for use by PCI devices; as a result, most of the PCI devices share legacy IRQ’s. In SMP mode, the I/O
APICs are used instead of the legacy “8259-style” interrupt controller. There is very little interrupt sharing
in SMP mode.
8.3.2 PnP ISA Auto-configuration
The system BIOS:
A Supports relevant portions of the Plug and Play ISA Specification, Revision 1.0a and the Plug and
Play BIOS Specification, Revision 1.0A.
B Assigns I/O, memory, direct memory access (DMA) channels, and IRQs from the system
resource pool to the embedded PnP Super I/O device.
C Does not support add-in PnP ISA devices.
8.3.3 PCI Auto-configuration
The system BIOS supports the INT 1Ah, AH = B1h functions, in conformance with the PCI Local Bus
Specification, Revision 2.1. The system BIOS also supports the 16 and 32-bit protected mode interfaces
as required by the PCI BIOS Specification, Revision 2.1.
Beginning at the lowest device, the BIOS uses a “depth-first” scan algorithm to enumerate the PCI buses.
Each time a bridge device is located, the bus number is incremented and scanning continues on the
secondary side of the bridge before all devices are scanned on the current bus. The BIOS then scans for
PCI devices using a “breadth-first” search – all devices on a given bus are scanned from lowest to highest
before the next bus number is scanned.
System BIOS POST maps each device into memory and/or I/O space, and assigns IRQ channels as
required. The BIOS programs the PCI-ISA interrupt routing logic in the chipset hardware to steer PCI
interrupts to compatible ISA IRQs.
The BIOS dispatches any option ROM code for PCI devices to the DOS compatibility hole (C0000h to
DFFFFh) and transfers control to the entry point. The DOS compatibility hole is a limited resource;
therefore, system configurations with a large number of PCI devices may result in a shortage of this
resource. If the BIOS runs out of option ROM space, some PCI option ROMs are not executed and a
POST error is generated. Scanning PCI option ROMs may be controlled on a slot by slot basis in the
BIOS setup.