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ECB-865
ECB-865 User’s Manual 9
2.3.4 PCI Interface
The ICH2 PCI interface provides a 33 MHz, Rev. 2.2 compliant implementation. All PCI
signals are 5V tolerant, except PME#. The ICH2 integrates a PCI arbiter that supports up
to six external PCI bus masters in addition to the internal ICH2 requests.
2.3.5 IDE Interface (Bus Master Capability and Synchronous DMA Mode)
The fast IDE interface supports up to four IDE devices providing an interface for IDE hard
disks and CD ROMs. Each IDE device can have independent timings. The IDE interface
supports PIO IDE transfers up to 14 Mbytes/sec and Bus Master IDE transfers up 100
Mbytes/sec. It does not consume any ISA DMA resources. The IDE interface integrates
16x32-bit buffers for optimal transfers.
The ICH2’s IDE system contains two independent IDE signal channels. They can be
electrically isolated independently. They can be configured to the standard primary and
secondary channels (four devices). There are integrated series resistors on the data and
control lines.
Access to these controllers is provided by two standard IDC 40-pin connectors.
2.3.6 USB
The USB controller provides enhanced support for the Universal Host Controller Interface
(UHCI). This includes support that allows legacy software to use a USB-based keyboard
and mouse. The ICH2 is USB Revision 1.1 compliant. The ICH2 contains two USB Host
Controllers. Each Host Controller includes a root hub with two separate USB ports each,
for a total of 4 USB ports. The signals are provided by a 5 x 2 header or an optional USB
bracket adapter.
2.3.7 Ethernet
2.3.7.1 ICH2 LAN Controller
The ICH2’s integrated LAN Controller includes a 32-bit PCI controller that provides
enhanced scatter-gather bus mastering capabilities and enables the LAN Controller to
perform high speed data transfers over the PCI bus. Its bus master capabilities enable the
component to process high level commands and perform multiple operations; this lowers
processor utilization by off-loading communication tasks from the processor. Two large
transmit and receive FIFOs of 3 KB each help prevent data under runs and overruns while
waiting for bus accesses. This enables the integrated LAN Controller to transmit data with
minimum interframe spacing (IFS).
The LAN Controller can operate in either full duplex or half duplex mode. In full duplex
mode the LAN Controller adheres with the IEEE 802.3x Flow Control specification. Half
duplex performance is enhanced by a proprietary collision reduction mechanism.