Filter
Top Products
General Optimization Guidelines 2
2-51
Locality enhancement to the last level cache can be accomplished with
sequencing the data access pattern to take advantage of hardware
prefetching. This can also take several forms:
• Transformation of a sparsely populated multi-dimensional array into
a one-dimension array such that memory references occur in a
sequential, small-stride
1
, pattern that are friendly to the hardware
prefetch.
• Optimal tile size and shape selection can further improve temporal
data locality by increasing hit rates into the last level cache and
reduce memory traffic resulting from the actions of hardware
prefetching. (See “Hardware Prefetching and Cache Blocking
Techniques” in Chapter 6.)
It is important to avoid operations that work against locality-enhancing
techniques. Using the lock prefix heavily can incur large delays when
accessing memory, irrespective of whether the data is in the cache or in
system memory.
User/Source Coding Rule 6. (H impact, H generality) Optimization
techniques such as blocking, loop interchange, loop skewing and packing are
best done by the compiler. Optimize data structures to either fit in one-half of
the first-level cache or in the second-level cache; turn on loop optimizations in
the compiler to enhance locality for nested loops.
Optimizing for one-half of the first-level cache will bring the greatest
performance benefit in terms of cycle-cost per data access. If one-half of
the first-level cache is too small to be practical, optimize for the
second-level cache. Optimizing for a point in between (for example, for
the entire first-level cache) will likely not bring a substantial
improvement over optimizing for the second-level cache.
1. See “Data Prefetch” in Chapter 1