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IA-32 Intel® Architecture Processor Family Overview
1-9
• to operate at high clock rates and to scale to higher performance and
clock rates in the future
Design advances of the Intel NetBurst microarchitecture include:
• a deeply pipelined design that allows for high clock rates (with
different parts of the chip running at different clock rates).
• a pipeline that optimizes for the common case of frequently
executed instructions; the most frequently-executed instructions in
common circumstances (such as a cache hit) are decoded efficiently
and executed with short latencies
• employment of techniques to hide stall penalties; Among these are
parallel execution, buffering, and speculation. The
microarchitecture executes instructions dynamically and
out-of-order, so the time it takes to execute each individual
instruction is not always deterministic
Chapter 2, “General Optimization Guidelines,” lists optimizations to use
and situations to avoid. The chapter also gives a sense of relative
priority. Because most optimizations are implementation dependent, the
chapter does not quantify expected benefits and penalties.
The following sections provide more information about key features of
the Intel NetBurst microarchitecture.
Overview of the Intel NetBurst Microarchitecture Pipeline
The pipeline of the Intel NetBurst microarchitecture contains:
• an in-order issue front end
• an out-of-order superscalar execution core
• an in-order retirement unit
The front end supplies instructions in program order to the out-of-order
core. It fetches and decodes IA-32 instructions. The decoded IA-32
instructions are translated into micro-operations (µops). The front end’s
primary job is to feed a continuous stream of µops to the execution core
in original program order.