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IA-32 Intel® Architecture Optimization
6-40
happen to be powers of 2, aliasing condition due to finite number of
way-associativity (see “Capacity Limits and Aliasing in Caches” in
Chapter 2) will exacerbate the likelihood of cache evictions.
Example 6-9(b) shows applying the techniques of tiling with optimal
selection of tile size and tile width to take advantage of hardware
prefetch. With tiling, one can choose the size of two tiles to fit in the last
level cache. Maximizing the width of each tile for memory read
Example 6-9 Using HW Prefetch to Improve Read-Once Memory Traffic
a) Un-optimized image transpose
// dest and src represent two-dimensional arrays
for( i = 0;i < NUMCOLS; i ++) {
// inner loop reads single column
for( j = 0; j < NUMROWS ; j ++) {
// Each read reference causes large-stride cache miss
dest[i*NUMROWS +j] = src[j*NUMROWS + i];
}
}
b)
// tilewidth = L2SizeInBytes/2/TileHeight/Sizeof(element)
for( i = 0; i < NUMCOLS; i += tilewidth) {
for( j = 0; j < NUMROWS ; j ++) {
// access multiple elements in the same row in the inner loop
// access pattern friendly to hw prefetch and improves hit rate
for( k = 0; k < tilewidth; k ++)
dest[j+ (i+k)* NUMROWS] = src[i+k+ j* NUMROWS];
}
}